This paper discusses combined software and hardware architecture of a H. 264/AVC video compression decoder. The software version of the decoder was implemented using NIOS II processor on a FPGA board (Stratix III of Altera). The mixed, software and hardware, architecture was proposed to ameliorate the decoder speed throughputs. According to the time execution profiling and data dependencies, the decoder partitioning was applied. Thus, the inverse 4x4 Intra process is replaced by a hardware accelerator. It includes inverse 4x4 Intra prediction, inverse transform and inverse quantization. The experimental results at 317 MHz show improvement on the decoding throughput by 20% between software solution and mixed one.

Security and privacy are both involved in vehicular communications for successful adoption and deployment of the VANET. Generally, attacks cause anomalies to the network functionality. A secure Vehicular Ad Hoc Networks (VANET) system, while exchanging information should protect the system against unauthorized message injection, message alteration, eavesdropping. In this paper, we propose, an enhanced authentication protocol called MAVnet for Multilevel authentication protocol. The proposed protocol considers the different vehicle categories and guarantees authentication, where a third party is used, which is the Authentication, Authorization and Accounting (AAA) server. The MAVnet protocol is then carried out for tracking services by managing information using the DBMS (Database Management System). The main purpose of our work is to ensure the vehicle authentication, while respecting the constraints of vehicle categories by minimizing thing overhead of communications. Two ways of simulation are performed. The first one uses AVISPA framework, where simulation results of the protocol demonstrate that it is SAFE (according to AVISPA goals). And, the second simulation uses the Java Cryptography Extension (JCE) library. The simulation results show that the privacy can be maintained better by applying the proposed architecture and it's able to lessen the number of exchanging messages and time lag. The results show the superiority of MAVnet is significantly higher than that of the certificate-based authentication protocol and the identity-based authentication protocol.

Multiprocessor System on Chip (MPSoC) is a promising way to reduce the processing time required by digital multimedia encoders such the most complex H.264/Advanced Video Coding. MPSoC contributes in this challenge by offering a high performance computing, little system on chip (SoC) surface, and low power consumption. In order to reduce the execution time of H.264/AVC intra only encoding chain, an efficient parallel processing on MPSoC architecture is proposed in this paper. The proposed parallel processing is based on a mixed partitioning which combines slice and macro blocks line level parallelism. The proposed architecture is designed through SoCLib platform. For performances evaluation, three MIPS32 processors are used to accelerate the encoding time. Experimental results for High Definition (HD) video sequences show that the proposed implementation allows a saving of 65.7% in processing time compared to a single CPU execution. Furthermore, the proposed solution is characterized by a relatively low memory size which positively affects the final circuit surface.

There has been a growing interest in the reversible integer to integer wavelet transforms for image coding. In this paper, several of those particular transforms are integrated using a VHDL description on a FPGA circuit. Two different architectures are proposed, one uses the lifting framework as an architectural support and the other takes advantage of the two finite impulse response filter (FIR) structures representing the wavelet transform function. Evaluation is performed on the basis of their computational complexity, latency, hardware occupancy, and finally maximum operating clock frequency of the circuit obtained. Of the transforms considered, some of them seem to perform particularly well depending on the architecture used.

A common method for selecting the best prediction mode based on block matching algorithm is to compare, for each source block, the associated distortions among the available prediction candidates. The human visual perception is sensitive to luminance contrast rather than absolute luminance values. In fact, the human eyes ability to detect the magnitude difference between an object and its background depends on the background luminance average value. The Perceptually Weighted Distortion (PWD) is a new distortion measure that can produce better image quality. In this paper, we propose to add a new feature to the PWD by introducing another diagonal component that yields to a significant quality improvement. The enhanced PWD metric actually outperforms the original PWD and the SAD metric, according to the experimental results, especially in the aspect of reducing block artifacts. An increase in terms of implementation complexity will be noticed as a result of this contribution. Therefore, optimized implementation of the Enhanced PWD exploiting the C64 DSP-Core assets will be presented. In fact, Standard Assembly (SA) is used to implement the different Enhanced PWD functions in order to exploit efficiently the C64 internal architecture and resources. Experimental results show more than 85% improvement in terms of cycle cost compared to C code.

Summary Motion estimation and compensation techniques are widely used for video coding applications but the real-time motion estimation is not easily achieved due to its enormous computations. Therefore, it would be greatly beneficial to optimize as much as possible the motion estimation bloc which is considered to be the most important in terms of computational cost. In this paper, a new fast block size selection DSP-based algorithm is presented, in which computation complexity is greatly reduced when achieving the same video quality. Experimental results show a 45.75% improvement in speed with no major loss in video quality (objective (PSNR) and subjective (SSIM)).

Block matching motion estimation algorithms have been developed for very different applications in image processing. In recent years, the variable block-size (VBS) motion estimation has been widely employed to improve the performance of the block matching algorithm. In this paper, we compare the performance of several variable block-size motion estimation algorithms based on merge and split procedures, and we propose a new algorithm based on the zoom effect. Many experiments results validate our procedure and illustrate the advantages and performance of our proposed algorithm compared to others. Our algorithm will be denoted here and after as: Zoom Motion Estimation (ZME).

Motion estimation in video coding standards, such as H.264/AVC, is considered to be the most timeconsuming encoding module. Motion estimation is generally performed on a 16x16 block, although in H.264/AVC, 7 different block sizes (16x16, 16x8, 8x16, 8x8, 8x4, 4x8 and 4x4) are allowed. The aim of this paper is to optimise the implementation of the motion estimation algorithm on the Texas Instruments’ TMS320C64 DSP. Specifically, the goal is to use the C64 set of instructions in order to optimise the Sum of Absolute Differences (SAD) engine within the motion estimation and to take advantage of the Direct Memory Access (DMA) to reduce the cycle cost in loading data from external to internal memory. Standard Assembly (SA) is used to implement the different SAD functions in order to exploit the C64 internal architecture and resources efficiently. Experimental results shows more than 75% improvement in terms of cycle cost compared to C code for each function.

In motion estimation, the search patterns with different shape and size have a large consequence on the searching speed and quality of performance. A popular example is the full search (FS) algorithm. Nevertheless, the high computational complexity of the FS algorithm has motivated several faster search strategies. However, the FS allows a better quality. In this paper, we compare the performance of several motion estimation algorithms for H.264/AVC video coding such as the three-step search (TSS), diamond search (DS), small diamond search (SDS), cross diamond search (CDS), hexagon-based search (HEXBS), nearest-neighbors search (NNS), and we propose a new one called Horizontal Diamond Search (HDS). Simulations show that HDS is particularly faster and more accurate in some kinds of sequences. This algorithm is especially suitable for videoconferencing applications.

In this paper, we study the computational complexity of the intra prediction module for video coding software according to H.264/AVC standard. We analyze separately the complexity of each intra mode for the implementation on TMS320C64 platform. The intra prediction unit consists of predicting the block's pixels from their neighbors according to different directional modes (horizontal, vertical, ...) and others non-directional (DC, planar). For each mode, we compute the number of the executional sub-units (add, shift, load, store...). Together with the number of necessary cycles to execute every instruction and the functional units that can perform these instructions, we can deduce the complexity of every intra mode. To estimate the total complexity of the intra prediction process, we assume that the encoder tests all intra modes. The total cycle's account is estimated by multiplying the number of cycles of each mode by the number of blocks in the picture. Our results indicate that our methodology for the complexity analyses of the intra prediction unit of the H.264/AVC provides a good approximation with respect to the experimental results.

In MPEG and VCEG standards, motion estimation is used to eliminate the temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present the design of a motion estimation circuit and its hardware implementation on FPGA based on "full search block matching" algorithm according to H.263 standard. We specified, simulated, and synthesized SAD's engine with VHDL description. The proposed design is implemented on a "stratix" FPGA using EPIS10B672C6 component. Our simulations confirm the functionality of the algorithm using "ModelSim" simulator and synthesis using the "Quartus" software provided by ALTERA. This study represents a mean stone for FPGA implementation of motion estimation algorithms.

With the increasing usage of multimedia technologies, image compression requires higher performances as well as new features. To address these needs in the specific area of continuous tone still image encoding, a new standard is currently being developed, the JPEG2000. It is not only intended to provide rate-distortion and subjective image quality performance superior to existing standards, but also to provide new features and functionalities that current standards can either not address them efficiently or in many cases cannot address them at all. Copyright (C) 2004 AEI.

In this paper we present a new method to implement constant operand multiplier. The structure is optimized in point of view of surface occupation and time execution. The principle of the new method based on a compression of four partial products into one row. The method proofs its availability for both signed and unsigned multiplication. Simulation results using FPGA implementation technology show an improvement of proposed algorithm performances compared to DADDA multiplier.

There has been a growing interest in the reversible integer to integer wavelet transforms for image coding. In this paper, several of those particular transforms are integrated using a VHDL description on a FPGA circuit. Two different architectures are proposed, one uses the lifting framework as an architectural support and the other make advantage of the two finite impulse response filter (FIR) structures representing the wavelet transform function. Evaluation is done on the basis of their computational complexity, latency time, hardware occupancy, and finally maximum operating clock frequency of the circuit obtained. Of the transforms considered, some of them seem to perform particularly well depending on the relative importance of the preceding criteria.