Ruszt József a 20. század második felének meghatározó jelentőségű színházrendezője, -pedagógusa, társulatszervezője. Életművének feldolgozása és színházszemléletének megismerése a kortárs színháztörténet-írás feladata. Ruszt egész életművében kiemelkedően jelentősek, programszerűek voltak a magyar drámák, így Csokonai műveinek színrevitelei is. Ruszt erről így fogalmaz: „Szeretem a régi magyar irodalmat. Nemcsak nyelvét, gondolatvilágát, hanem – európai viszonylatban – páratlan vállalásait is szeretem, s úgy érzem, ez a vállalás ma is aktuális, igaz, nem ugyanazon okok miatt, mint annak idején.” Kutatásom Ruszt Csokonai-olvasatának aktualitását kísérli meg körüljárni az Egyetemi Színpadon 1965-ben bemutatott A’ özvegy Karnyóné-előadásának (re)konstrukciója során. Tanulmányom fókuszában három szempont áll: Mennyiben lehet meghatározója az egyetemi (színpadi) lét a színházi nyelvhasználat szabadságmozgalmának? Az Universitas Együttes előadása milyen, a korabeli realista-naturalista formakánont kijátszató formanyelvvel dolgozott? Hogyan válhatott éppen egy 18. századi magyar dráma előadása az Universitas társulatának egyik legnagyobb sikerű, nemzetközi elismerésben is részesülő előadásává?

In this paper, a novel tool and a methodology are introduced to create a thermally driven digital cell placement capability that considers the cooling capability of the integrated microscale heatsink structures. Normally, the realization of this kind of placement would require time-consuming computation fluid dynamics (CFD) simulations. With the presented solution, the CFD tool can be replaced by a thermal simulator, which incorporates analytical fluid dynamics compact models. By this approach, the determination of the precise local heat transfer coefficient(s) (thus cooling efficiency) can be realized. In addition, the temperature distribution along the microchannels can also be obtained depending on the channel geometries, the thermal properties of the fluid and the wall temperature(s). While this model is integrated into the thermal simulator, it is still needed to be connected to commercial digital IC design tools to unleash its full potential. Therefore, the interfacing tool is also developed that launches either the thermal, the electrical, or logical simulators and placement programs by using the outputs (results) of the other programs as the inputs.

Smart systems - according to a simplistic definition - provide new qualities and new functionalities through the integration of formerly distinct functions, components and networks. Street-lighting (as other lighting applications) recently went already through a drastic change offered by "LEDification". The easy electronic controllability of LEDs as light sources triggered a new change of paradigm: integration of LED based luminaires into smart systems. Smart integration necessitates among others both adaptability to the environmental conditions and intelligent remote control that require a communications systems based on a multi-layer data transfer protocol. We are reporting about an ongoing project that targets a "future proof" solution which is not restricted to lighting control but allows public lighting installations to play key roles in other smart city functions needed in outdoor public spaces such as communications with vehicles. The result of the development is a new IoT device which can be installed in street-lighting luminaires and allows physical layer (e.g. PLC, WiFi, ZigBee or other RF transmission) independent data transfer. The main functionality of the application layer of the protocol remains of course lighting control which is best implemented on the basis of existing standards (such as DALI), but the system allows the implementation of other communications tasks based on other application layer protocols.

In the framework of the first revision of toll rates calculated before the launch of the HU-GO truck toll collection system in Hungary, in July 2013, the re-determination of the infrastructure costs related to the tolled road network became necessary. Replacement costs of the main road components (considered as being a substitute of asset values) were to be calculated using the so called Synthetic Method, since the net asset values of the tolled road networks weren’t recorded separately in the books of the national road administration. Basic assumptions as well as main steps and results of the calculation of replacement cost (asset value), as well as of the average depreciation key are presented and some relevant conclusions are formulated.

This paper proposes a methodology to simulate temperature dependent timing in standard cell designs. Temperature dependent timing characteristics are derived from standard delay format (SDF) files that are created by synthesis tools automatically. A case study is also presented in this paper where the temperature dependent frequency variation of a ring oscillator is simulated demonstrating the necessity of temperature dependent timing simulations. An adaptively refineable partitioning method for simulating standard cell designs logi-thermally is proposed as well. This paper also introduces recent enhancements in the CellTherm logi-thermal simulator developed in the Department of Electron Devices, BME, Hungary.

In today's digital electronic integrated circuits device heating is one of the most critical issues. Overheating can cause failures in functionality and device malfunction. In certain circumstances overheating of ICs can cause physical destruction of the device itself. This paper introduces a solution to determine cell and gate heating curves across the standard cell IC's surface. The presented methodology and toolset is tightly integrated into standardized logic simulator engines thus providing digital circuit designers a low-level, cell-resolution temperature distribution map during logic simulations. Actual temperatures of each consisting cell of the design can be monitored throughout the whole logic simulation. By being able to monitor temperatures of digital cells during initial simulations, it allows us to detect hot-spots and overheating caused malfunctions far before manufacture. By using the spatial location and temperature magnitude of hot-spots acquired from the presented methodology, place and route (P&R) tools can be driven to change cell placement and routing in order to avoid heating caused failures. Additionally, cooling solutions can be developed using the simulated temperature maps of the IC's surface. This paper also presents various aspects of power characterization methods which were used throughout the experiments.

This paper introduces a new temperature dependent timing model that allows designers to deal with accurate temperature dependent delays in logic simulations. In this proposal we present the latest enhancements in the CellTherm logi-thermal simulator developed in the Department of Electron Devices, BME, Hungary. With the proposed accurate temperature dependent timing model thermal effects affecting delays in digital standard cell integrated circuits can be modeled with delay-temperature functions. In order to establish the model preliminary delay-temperature characterization is needed for the standard cells building up the circuit. We propose the extension of the industry standard Liberty format developed by Synopsys with the new model. With the new accurate model we demonstrate that present temperature-timing models do not describe temperature dependent operation sufficiently. In our presented model timing and power data can be parameterized by temperature vectors. It is also demonstrated that taking temperature dependent delays into account allows for more precise power modeling that is critical in low-power nanometer integrated systems.

This paper proposes an accurate temperature dependent delay model for logi-thermal simulations. During the logi-thermal simulation of digital integrated circuits the propagation delays of the standard cells can be calculated from delay-temperature functions. The delay-temperature functions contain exact and precise delay values for each input-output path and temperature value. Temperature characterization corners can be specified in arbitrary fine granularity and range. The model presented in this paper overcome the limitation of the classic SDF (Standard Delay Format) models in that propagation delay values can be given for arbitrary temperatures, not only a few corners. With classic SDF, temperature dependence of timing and thus power can only be taken into account for a few design corners. Between characterization corners, like supply voltage, process variation and temperature, linear interpolation must be used for intermediate data. With our proposed delay model temperature-aware timing simulations would produce more accurate results than the classic SDF model. This paper compares the classic SDF delay model with our temperature dependent detailed model and provides evidence through a simple example for the necessity of temperature-aware timing simulation. The logi-thermal simulations are carried out with the CellTherm[1] application developed in the Dept. of Electron Devices, BME, Hungary. A logi-thermal acceleration technique is also introduced in this paper.

This paper introduces a new temperature dependent timing model that allows designers to deal with accurate temperature dependent delays in logic simulations. In this proposal we present the latest enhancements in the CellTherm logithermal simulator developed in the Department of Electron Devices, BME, Hungary. With the proposed accurate temperature dependent timing model thermal effects affecting delays in digital standard cell integrated circuits can be modeled with delay-temperature functions. In order to establish the model preliminary delay-temperature characterization is needed for the standard cells building up the circuit. We propose the extension of the industry standard Liberty format developed by Synopsys with the new model. With the new accurate model we demonstrate that present temperature-timing models do not describe temperature dependent operation sufficiently. In our presented model timing and power data can be parameterized by temperature vectors. It is also demonstrated that taking temperature dependent delays into account allows for more precise power modeling that is critical in low-power nanometer integrated systems. I. WEAKNESSES OF PRESENT TIMING MODELS The timing information of standard cells in today’s integrated circuit design systems are stored in different databases. Most typically the timing and delay data of a standard cell library are stored in a Liberty database [1], [2] that circuit design applications use during synthesis and place&route (P&R). Logic simulators use the preor post-layout timing databases generated by the synthesizer applications for timing simulations. These timing data are usually stored in Standard Delay Files (SDF) [3]. The SDF files are generated by the synthesizer softwares during synthesis and P&R from the Liberty database. In the Liberty database, the delays and timing arcs of the standard cells are stored in a parametric form. This means that timing data in the Liberty file are characterized and stored for numerous input slew, load capacitance parameters. This way the synthesizer can calculate delays for the cells in the design according to the actual placement and routing. With each placement and routing scenario different SDF data are calculated for different layouts. This allows for accurate logic and timing simulations where actual layout topologies are taken into account. The disadvantage of the mentioned timing model is that the cell libraries are characterized on previously established and fixed process, voltage and temperature (PVT) corners [4]–[6]. The characterized data are valid for those certain corners thus for other corners a re-characterization is needed. The Composite Current Source (CCS) model developed by Synopsys [1], [7] addresses the problem of voltage and process parameter scaling by storing current waveforms in the Liberty database [8] rather than derived quantities like power or energy. On the other hand, the CCS model neither takes ambient and self-temperature variations into account that is necessary for temperature dependent delay simulations. Neither the former Non-Linear Delay Model (NLDM) nor the Scalable Polynomial Delay Model take device temperatures accurately into account. These limitations mean that a re-characterization is needed for the cell library for each temperature corner. With present models, delay changes caused by temperature variations can only be determined accurately at the characterized corners. On other temperatures delay values can be calculated with linear interpolation. However, cell delays calculated with linear interpolation can be inaccurate. More precise temperature dependence of delays can be achieved by characterizing delays in a wide temperature range with sufficient resolution (e.g. 1 ◦C). By characterizing the cell library for a wide temperature range with high resolution more precise timing and logithermal simulation results can be achieved. Timing, switching activity, power and temperature depend mutually on each other, since with varying delays switching activity changes in a unit time slot, that causes the change of dynamic power consumption that affects device temperature. Moreover, changing temperature modifies timing. In this paper we propose a new timing model in which we characterize propagation delays in a standard cell library in a wide temperature range with high resolution. The temperature dependent delays of the cells can be taken into consideration by the characterized delay-temperature curves. With the proposed model the thermal behavior of a standard cell design can be described precisely. The presented model can be easily integrated into the Liberty database which can effectively store multi-dimensional functions. II. GENERATION AND DESCRIPTION OF THE NEW MODEL We describe the creation of the new model step-by-step. Figure 1. helps the comprehension of the model generation flow.

In today's digital electronic integrated circuits device heating is one of the most critical issues. Overheating can cause failures in functionality and device malfunction. In certain circumstances overheating of ICs can cause physical destruction of the device itself. This paper introduces a solution to determine cell and gate heating curves across the standard cell ICs surface. The presented methodology and toolset is tightly integrated into standardized logic simulator engines thus providing digital circuit designers a low-level, cell-resolution temperature distribution map during logic simulations. Actual temperatures of each con- sisting cell of the design can be monitored throughout the whole logic simulation. By being able to monitor temperatures of digital cells during initial simulations, it allows us to detect hot-spots and overheating caused malfunctions far before manufacture. By using the spatial location and temperature magnitude of hot-spots acquired from the presented methodology, place and route (P&R) tools can be driven to change cell placement and routing in order to avoid heating caused failures. Additionally, cooling solutions can be developed using the simulated temperature maps of the ICs surface.

Regarding thermal issues in digital IC design a major concern is how timing integrity is affected by the elevated junction temperature and temperature gradients on the chip surface. To predict this in a thermal aware design process one needs a dedicated simulation tool in which the logic simulation of the circuit is coupled to the thermal simulation of the chip and its environment. This paper presents two approaches to this so called logithermal simulation. In one of our approaches we rely completely on industry standard EDA tools, standard EDA file formats and interfaces. In the other solution which provides us total freedom in the abstraction level of circuit description and simulation accuracy we use our own logic simulation engine. In both cases the logic simulation engine is connected to our own thermal simulation engines which also use compact thermal models of the IC package during simulation. This paper describes certain implementation aspects and features of our logithermal simulation solutions, with emphasizes on modeling the thermal properties of the IC packaging.

This paper proposes a method for yield enhancement in digital integrated circuit manufacture using a temperature dependent logic simulation tool.In an industrial environment the time slot dedicated to the logic testing of a single integrated circuit needs to be as short as possible in order to boost production. During this short period thermally induced errors might remain hidden due to long thermal time constants.This paper introduces a methodology to determine the steady-state die temperature where a short logic test is able to reveal logic faults. The evolved die temperature is simulated with a logi-thermal simulator engine that performs logic simulation by taking self-heating into account.We propose that the testing should take place at an elevated temperature where the temperature dependent failures arise. This approach makes it possible to detect otherwise hidden defects while keeping testing times short.

Thermal (side-)effects can detrimentally influence operation of integrated circuits. The increase of temperature changes the devices' characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology as well as a tool to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also briefly presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperature-dependent delays during the running simulation.

The paper presents some preliminary results of an on-going research aiming to assess expected impacts of climate change on road infrastructure planning, design and operation, as well as determining what measures could be considered and recommended to manage these potential impacts. Following an overview of the main parameters (temperatures and precipitation) characterizing expected climate change in the period of 2071–2100, the impacts on roads of high temperatures, freeze-thaw cycles, prolonged growing season, high intensity precipitation, wet conditions and flooding are studied. According to the author, the anticipated effects of climate change should be manageable with current, or slightly modified engineering practice and the materials available, possibly with adaptation. Recommendations are formulated concerning the adaptation process.

In this paper a new approach for measuring depth values of cavities of Micro-Electro Mechanical System (MEMS) is presented. This measurement was done by using a simple optical microscope and image processing techniques. The sample need not to be treated with any foreign material such as reflective or conductive coating.