The setup includes a host PC, camera and microphone sensors, and a Pynq-Z2 FPGA board. The neuromorphic cochlear model and RAMAN accelerator for neural network inference are deployed on the FPGA. The ARM processor on the FPGA sends the image received, cochleagram and the classified outputs to the PC to be visualized.

Deep Neural Network (DNN) based inference at the edge is challenging as these compute and data-intensive algorithms need to be implemented at low cost and low power while meeting the latency constraints of the target applications. Sparsity, in both activations and weights inherent to DNNs, is a key knob to leverage. In this paper, we present RAMAN, a Re-configurable and spArse tinyML Accelerator for infereNce on edge, architected to exploit the sparsity to reduce area (storage), power as well as latency. RAMAN can be configured to support a wide range of DNN topologies - consisting of different convolution layer types and a range of layer parameters (feature-map size and the number of channels). RAMAN can also be configured to support accuracy vs power/latency tradeoffs using techniques deployed at compile-time and run-time. We present the salient features of the architecture, provide implementation results and compare the same with the state-of-the-art. RAMAN employs novel dataflow inspired by Gustavson's algorithm that has optimal input activation (IA) and output activation (OA) reuse to minimize memory access and the overall data movement cost. The dataflow allows RAMAN to locally reduce the partial sum (Psum) within a processing element array to eliminate the Psum writeback traffic. Additionally, we suggest a method to reduce peak activation memory by overlapping IA and OA on the same memory space, which can reduce storage requirements by up to 50%. RAMAN was implemented on a low-power and resource-constrained Efinix Ti60 FPGA with 37.2K LUTs and 8.6K register utilization. RAMAN processes all layers of the MobileNetV1 model at 98.47 GOp/s/W and the DS-CNN model at 79.68 GOp/s/W by leveraging both weight and activation sparsity.

The growing use of acoustic classification systems in edge computing and Internet of Things (IoT) devices has created a demand for innovative technologies and methods that can deliver high performance and energy efficiency. In this work, we introduce a novel audio inference system that combines RAMAN, a Re-configurable and spArse tinyML Accelerator for infereNce, with a hardware-efficient Neuromorphic cochlea for pre-processing. The neuromorphic cochlea mimics human hearing, specifically by employing the ‘Cascade of Asymmetric Resonators (CAR)’ model to replicate the basilar membrane filter in the human cochlea. In this study, we utilize a 30 cascaded-filter cochlear section to process real-time audio data and a RAMAN classifier for audio classification. RAMAN leverages activation and weight sparsity within the neural network to reduce storage, latency, and power consumption. The proposed audio inference system has been implemented on a Microchip MPFS250T SoC field-programmable gate array (FPGA) with 52.57k LUTs, all while operating with a power consumption of 237.3 mW at 40 MHz clock frequency. The proposed audio inference system is designed for low-power auditory edge applications such as speaker verification, speech detection, and keyword spotting.

Despite advances in understanding the mechanisms of movement disorders, controlling voluntary movements remains challenging, with limited treatment options. However, the integration of machine learning (ML) accelerators into the braincomputer interface (BCI) pipeline offers promising solutions by harnessing the capabilities of ML algorithms to decode intended motor actions accurately. While there have been numerous efforts to classify intended hand movements into discrete classes, the challenging problem of decoding continuous hand kinematics has seen limited research efforts. Our work focuses on tackling this challenge using RAMAN, an energy-efficient tinyML accelerator. We demonstrate the successful decoding of macaque hand kinematics from the MC_Maze dataset on the Efinix Ti60 FPGA with RAMAN architecture. Our approach achieves an R2-score of 0.91 across 108 different maze configurations with a significantly low memory footprint of 230 KB, a latency of 86.7 ms while consuming 52.23 mW of power at a 5 MHz clock rate and 5.78 ms latency with the peak power efficiency of 102.34 GOp/s/W at 75 MHz and 75% pruning.

The setup includes a host PC, microphone, and FPGA board. The CAR model and RAMAN are implemented on the FPGA, while the maze game and cochleagram visualization software run on the PC. The microphone captures sound from its surrounding environment and transmits the audio data to the FPGA bit-by-bit. The I 2 S (Inter-IC Sound) module combines this data into 16-bit audio samples and forwards it to the CAR model. The output from the CAR model is then fed into RAMAN. The outputs from the CAR model and RAMAN are transferred to the host PC via Arduino Nano 33 BLE to control the maze game.

We present the design and performance of the GROWTH-India telescope, a 0.7 m robotic telescope dedicated to time-domain astronomy. The telescope is equipped with a 4k back-illuminated camera giving a 0.82-degree field of view and sensitivity of m_g 20.5 in 5-min exposures. Custom software handles observatory operations: attaining high on-sky observing efficiencies (> 80 and allowing rapid response to targets of opportunity. The data processing pipelines are capable of performing PSF photometry as well as image subtraction for transient searches. We also present an overview of the GROWTH-India telescope's contributions to the studies of Gamma-ray Bursts, the electromagnetic counterparts to gravitational wave sources, supernovae, novae and solar system objects.

Particle filtering is very reliable in modelling non-Gaussian and non-linear elements of physical systems, which makes it ideal for tracking and localization applications. However, a major drawback of particle filters is their computational complexity, which inhibits their use in real-time applications with conventional CPU or DSP based implementation schemes. The re-sampling step in the particle filters creates a computational bottleneck since it is inherently sequential and cannot be parallelized. This paper proposes a modification to the existing particle filter algorithm, which enables parallel re-sampling and reduces the effect of the re-sampling bottleneck. We then present a high-speed and dedicated hardware architecture incorporating pipe-lining and parallelization design strategies to supplement the modified algorithm and lower the execution time considerably. From an application standpoint, we propose a novel source localization model to estimate the position of a source in a noisy environment using the particle filter algorithm implemented on hardware. The design has been prototyped using Artix-7 field-programmable gate array (FPGA), and resource utilization for the proposed system is presented. Further, we show the execution time and estimation accuracy of the high-speed architecture and observe a significant reduction in computational time. Our implementation of particle filters on FPGA is scalable and modular, with a low execution time of about 5.62 μs for processing 1024 particles (compared to 64 ms on Intel Core i7-7700 CPU with eight cores clocking at 3.60 GHz) and can be deployed for real-time applications.

The mammalian spatial navigation system is characterized by an initial divergence of internal representations, with disparate classes of neurons responding to distinct features including location, speed, borders and head direction; an ensuing convergence finally enables navigation and path integration. Here, we report the algorithmic and hardware implementation of biomimetic neural structures encompassing a feed-forward trimodular, multi-layer architecture representing grid-cell, place-cell and decoding modules for navigation. The grid-cell module comprised of neurons that fired in a grid-like pattern, and was built of distinct layers that constituted the dorsoventral span of the medial entorhinal cortex. Each layer was built as an independent continuous attractor network with distinct grid-field spatial scales. The place-cell module comprised of neurons that fired at one or few spatial locations, organized into different clusters based on convergent modular inputs from different grid-cell layers, replicating the gradient in place-field size along the hippocampal dorso-ventral axis. The decoding module, a two-layer neural network that constitutes the convergence of the divergent representations in preceding modules, received inputs from the place-cell module and provided specific coordinates of the navigating object. After vital design optimizations involving all modules, we implemented the tri-modular structure on Zynq Ultrascale+ field-programmable gate array silicon chip, and demonstrated its capacity in precisely estimating the navigational trajectory with minimal overall resource consumption involving a mere 2.92% Look Up Table utilization. Our implementation of a biomimetic, digital spatial navigation system is stable, reliable, reconfigurable, real-time with execution time of about 32 s for 100k input samples (in contrast to 40 minutes on Intel Core i7-7700 CPU with 8 cores clocking at 3.60 GHz) and thus can be deployed for autonomous-robotic navigation without requiring additional sensors.

Bayesian models are challenging to implement on hardware with the conventional design methodologies due to their high computational complexity. Conventional digital architectures are designed for deterministic computation and are not optimal for implementing probabilistic algorithms on hardware. In this work, we propose an alternative method to implement the probabilistic algorithms such as Bayesian models on hardware using a stochastic computation (SC) framework. This framework leverages on the probabilistic nature of the Bayesian models and facilitates the implementation of complex probabilistic models using simple logic gates. From an application standpoint, we propose a novel Bayesian source localization model (BSLM) that estimates a source's position in a noisy environment by solving the Bayesian recursive equation implemented on Field Programmable Gate Array (FPGA) with low resource utilization. The proposed SC design framework will pave the way to build complex probabilistic algorithms for real-time edge computing applications.

The space-based automatic identification system (S-AIS) is a maritime safety and vessel monitoring system used to broadcast the ship position and other telemetry every few seconds in short bursts. A satellite-based AIS receiver is of interest to defense community as it provides global or wide-area coverage. However, when the satellite passes regions with elevated traffic density, a major challenge is to overcome the message or signal interference at the satellite receiver. This paper mainly focuses on developing a novel AIS satellite receiver that uses fast independent component analysis (FastICA) blind source separation technique to resolve the overlapped signals at the satellite. We propose an architecture to realize FastICA algorithm on hardware. In addition to this, we present Gaussian minimum shift keying modulator and demodulator design schemes used by the S-AIS transponders. The proposed framework is realized on Virtex5-xc5vlx110t field-programmable gate array. The results obtained validate the effectiveness of the FastICA architecture realized by recovering the original ship data from the overlapped signals.

This study aims to record and translate the process of motor imagery to enable orthotic extension and flexion of the finger. This study probes the feasibility of developing a Brain Computer Interface system by prioritizing - Data Acquisition, Deep Learning, and End Effector of the system. The optimal channels to record MI data were deduced using Recursive Feature Elimination from a sixty four channel online dataset. Eight electrode channels of the OpenBCI Cyton kit were used, covering the sensorimotor cortex region of five subjects to record electroencephalographic data by following a standardized EEG acquisition protocol. Classification of tasks was carried out on a custom deep learning architecture using a convolutional layer and LSTM. The results were passed to an orthotic brace that provided a kinesthetic feedback mechanism to improve grip strength and support the neurorehabilitation of its user.

Particle filtering is a recursive Bayesian estimation technique that has gained popularity recently for tracking and localization applications. It uses Monte Carlo simulation and has proven to be a very reliable technique to model non-Gaussian and non-linear elements of physical systems. Particle filters outperform various other traditional filters like Kalman filters in non-Gaussian and non-linear settings due to their non-analytical and non-parametric nature. However, a significant drawback of particle filters is their computational complexity, which inhibits their use in real-time applications with conventional CPU or DSP based implementation schemes. This paper proposes a modification to the existing particle filter algorithm and presents a highspeed and dedicated hardware architecture. The architecture incorporates pipelining and parallelization in the design to reduce execution time considerably. The design is validated for a source localization problem wherein we estimate the position of a source in real-time using the particle filter algorithm implemented on hardware. The validation setup relies on an Unmanned Ground Vehicle (UGV) with a photodiode housing on top to sense and localize a light source. We have prototyped the design using Artix-7 field-programmable gate array (FPGA), and resource utilization for the proposed system is presented. Further, we show the execution time and estimation accuracy of the high-speed architecture and observe a significant reduction in computational time. Our implementation of particle filters on FPGA is scalable and modular, with a low execution time of about 5.62 us for processing 1024 particles and can be deployed for real-time applications.

Analog-to-digital converters (ADCs) provide the link between continuous-time signals and their discrete-time counterparts, and the Shannon-Nyquist sampling theorem provides the mathematical foundation. Real-world signals have a variable amplitude range, whereas ADCs, by design, have a limited input dynamic range, which results in out-of-range signals getting clipped. In this paper, we propose an unlimited dynamic range ADC (UDR-ADC) that is based on the modulo operation (self-reset feature) to alleviate the problem of clipping. The self-reset feature allows for wrapping of the input amplitudes, which preserves the input dynamic range. We present the signal model and a reconstruction technique to recover the original signal samples from the modulo measurements. We validate the operation of the proposed ADC using circuit simulations in 65 nm complementary metal-oxide-semiconductor (CMOS) process technology. The validation is supplemented by a hardware prototype designed using discrete components. A performance assessment in terms of area, power requirement, and the signal-to-quantization-noise ratio (SQNR) shows that the UDR-ADC outperforms the standard ones.

The Automatic Identification System (AIS) is an automated tracking system used for exchanging static and dynamic vessel information between the AIS terminals. Data transmitted by the AIS station is received by other vessel or base station. But due to the range limitations in the ground-based network, we go for Space-based Universal ship-borne Automatic Identification System (S-AIS) wherein the AIS-Data is received by satellite for the global coverage. In this paper, we present the performance analysis of the space-based AIS system considering the Field of View (FoV) of the satellite spanning a large number of Self-Organizing Time Division Multiple Access (SOTDMA) clusters and implementation of AIS Modem using SOTDMA scheme with Gaussian Minimum Shift Keying (GMSK) modulation. The introduction of reconfigurable devices and high level hardware description languages have made the design of AIS modem to be implemented efficiently on Virtex5-xc5vlx110t FPGA. The system is optimized in terms of hardware utilization. The SOTDMA architecture is designed at the Behavioral level of abstraction with constraints as defined by International Telecommunication Union (ITU) and is implemented using Verilog Hardware Description Language (HDL) on the FPGA, GMSK modulator and demodulator is designed in Xilinx System Generator. The SOTDMA architecture implemented is tested by considering multiple users to verify the unique slot allocation within a SOTDMA cluster. The FPGA implementation results are presented.

AbstractA CanSat is a simulation of a real satellite, integrated within the volume and shape of a cylindrical structure. The challenge is to fit all the major subsystems found in a satellite, such as power, sensors and a communication system into this minimal volume. The CanSat is then launched to an altitude of few hundred meters by a rocket or dropped from a platform or captive balloon and its mission begins: To carry out a scientific experiment and achieve a safe landing. CanSat is composed of a Carrier and a Lander. Carrier's objective is to measure and transmit variation in Hydrogen gas concentration; change in temperature; altitude by non GPS system; GPS coordinates during its descent. Release of Lander from Carrier at an altitude of 150 m from ground, imaging in the nadir direction is the Lander's mission.