In this paper, we present a wideband high-gain low-noise amplifier (LNA) with dual transformer feedback and current-reuse techniques. The first and second stages utilize a current-reuse technique to minimize low power consumption, while the third stage employs a cascode structure for high gain. Dual transformer feedback is applied to the first and second stages to suppress high-frequency gain roll-off, thereby extending the bandwidth. This paper proposes an improved transformer structure, which achieves compact footprint and higher coupling coefficient compared to traditional coupled-line implementations. The proposed wideband LNA is fabricated in 0.15-μm GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process. The measured results show that the proposed LNA achieves a gain of 25.1 dB with a 3-dB bandwidth of 8-19 GHz. The LNA exhibits output 1 dB compression point (OP1dB) of 9 dBm, a minimum noise figure of 1.56 dB, and an S11 value of less than -10 dB across the entire operating bandwidth. The fabricated LNA consumes 84 mW and occupies a chip area of 1.13 mm2 including test pads.
Addressing the critical need for polar decoders that can deliver both high throughput and superior error performance, Belief Propagation with Flipping (BPF) has been studied as an effective scheme. However, the extensive number of processing units (PEs) in traditional BPF decoders results in significant circuit area. To overcome the limitation, this work proposes a Sensitivity-Aware Look-Up Table (LUT)-based Belief Propagation with Flipping (SAL-BPF) decoder, where complex arithmetic functions are replaced by LUTs with message sensitivity analysis. This approach greatly reduces computational complexity and memory access with negligible frame error rate (FER) performance degradation. The proposed SAL-BPF polar decoder with 1024 bit length and 1/2 rate is Synthesized with 28nm CMOS technology. It shows that the proposed LUT-based processing element (PE) achieves over 44% area reduction and 17% delay savings compared with conventional arithmetic PE, with less than 0.35 dB FER performance degradation. The proposed SAL-BPF polar decoder with 6-bit quantization, achieving 1.33 GHz maximum frequency and 0.508 mm2 area. It achieves an excellent trade-off between decoding performance and hardware efficiency.
Time-domain computing-in-memory (CIM) has gained widespread attention in the acceleration of neural network due to its high energy efficiency and large signal margin. However, conventional time-domain CIM architectures face several limitations, including inefficient utilization of sparsity as well as accuracy degradation caused by PVT (process, voltage, temperature) variations, and the high energy and delay overhead of shift-and-add circuits. To address these issues, this work presents a time-domain CIM macro featuring: (1) a zero-weight skipping delay-chain structure that reduce MAC energy and delay by 88.2% and 82.5%, respectively; (2) a self-calibration circuit that reduces offset by 95%; and (3) a shift-and-add embedded time-to-digital converter (TDC) that lowers macro energy consumption and latency by 22.3% and 16.4%, respectively. Evaluation based on the implemented macro shows that when executing VGG16, ResNet-18, and GoogLeNet, the proposed design improves energy efficiency by factors of 1.68×, 2.86×, and 3.18×, and reduces latency by 63.3%, 82.9%, and 91.8%, respectively.
Combinatorial Optimization Problems (COPs) are prevalent across many fields and are mostly NP-hard, posing significant challenges for conventional von Neumann architectures. Ising machines offer a promising alternative by mapping COPs onto spin systems that evolve toward low-energy states. Recent efforts have implemented Ising machines using various technologies, yet silicon-based approaches often suffer from limited parallelism and high energy consumption due to data movement and complex digital sampling. In this paper, we propose a memristor-based Ising machine scheme enhanced by probabilistic neurons that enable analog in-memory annealing. By performing spin updates directly in the analog domain, our architecture eliminates the need for high-precision ADCs and integrates intrinsic stochasticity for efficient exploration of the solution space without extra cost. Our proposed scheme can be easily integrated into existing memristor-based Ising machines and achieves approximately 100% improvement in energy efficiency.
In this work, we investigate the application of Knowledge Distillation (KD) to the Quantum Approximate Optimization Algorithm (QAOA) setting, introducing a framework to distill knowledge from a Multi-angle QAOA teacher to a standard, single-layer QAOA student. We propose three distillation schemes: count-based KD, distillation using MSE, and distillation with Huber loss for enhanced robustness. Numerical experiments on diverse graph families, including complete graphs, Erdős–Rényi graphs, complete binary trees, and random 3-regular graphs, suggest that MSE and Huber-based distillation can improve the student’s performance, while count-based KD exhibits higher variance and limited generalization. Our results indicate that KD can enable a compression of the QAOA parameter space while often maintaining competitive solution quality, providing a practical avenue for efficient deployment on Noisy Intermediate-Scale Quantum hardware with improved training stability.
Attention deficit hyperactivity disorder (ADHD) diagnosis using functional magnetic resonance imaging (fMRI) data has grown increasingly prevalent with advances in deep learning. However, most research has focused on symptom-based subtyping of ADHD, which fails to address the intrinsic heterogeneity of this disorder. To address this limitation, we propose an end-to-end deep learning framework for ADHD biotype identification, which integrates feature learning and the clustering process by combining a variational autoencoder model with pseudo-label assignment modules. This unified architecture facilitates mutual reinforcement between feature learning and clustering optimization. Two distinct ADHD biotypes cluster with clear separation from healthy controls and from each other. Meanwhile, linear regression tests reveal significant associations between these biotypes and symptom-based subtypes, enhancing the understanding of the biological mechanisms underlying symptomatic manifestations. The proposed framework offers an effective solution for ADHD biotype identification, providing valuable insights for personalized ADHD treatment.
Approximate discrete cosine transform (DCT) accelerators are widely employed in energy-constrained image, video, and audio processing systems, where application-specific quality requirements enable aggressive optimization. This work presents a fully synthesizable approximate DCT architecture that exploits scaling factor optimization to minimize area and energy for a specified quality target. A random forest regression model is trained to quantify the relative importance of scaling factors associated with each DCT coefficient, guiding efficient design-space exploration and selection of optimal configurations. Furthermore, activity masking is introduced to dynamically adjust the number of active DCT coefficients, allowing real-time adaptation of energy consumption to varying quality demands. The 8X8 DCT architectures implemented in a 28nm CMOS process achieve 8–35% energy reduction and 13–57% improvement in energy–delay product (EDP) compared to state-of-the-art designs at iso/higher-quality. These gains will scale substantially at the system level, where the DCT core is repeatedly invoked for block-based transforms in medium- and high-resolution image and audio processing workloads.
Architectural simulators are widely used in computer architecture to explore design spaces and validate ideas before implementation. Recent works such as Scale-Sim extend this approach to convolutional neural network (CNN) accelerators, particularly systolic array-based designs. However, most target ASIC and overlook the unique resource characteristics of FPGA which is now a popular platform for CNN acceleration. To address this gap, we present MoSim, a modular, cycle-accurate simulator tailored for FPGA-based systolic CNN accelerators. MoSim models FPGA-specific resources and reports detailed performance and resource statistics to facilitate design space exploration. Evaluations on representative CNN workloads demonstrate that the simulator effectively captures FPGA-specific effects and guides practical design decisions.
In-memory computing based on memristive devices is highly promising, yet the overheads of gradient-based learning pose challenges for post-deployment adaptation/finetuning or on-chip training. Model-agnostic meta-learning (MAML) overcomes this challenge by providing a good initialization of the memristive conductances, which can be further tuned online to suit a particular task. We propose an efficient on-chip adaptation technique for finetuning MAML models on the memristive hardware. We first prepare the models for on-chip deployment by training on high-precision hardware. Further, we simplify the on-chip adaptation process by using the delta learning rule, which updates only the last layer of the model. We tested our approach on the DoubleMNIST and Omniglot datasets on non-ideal memristive hardware. Our methods for on-chip adaptation reduce area, latency, and energy by up to 18%, 61%, and 90%, respectively, while reducing accuracy by < 1.0%.
This paper presents an ultra-low-power, high-output-power, and high-sensitivity transceiver for implantable bioelectronic systems in a 40-nm CMOS technology. The design targets stringent power constraints by employing a wake-up scheme. The transceiver introduces a transmitter architecture based on a cascaded injection-locked ring oscillator (ILRO) and edge combiner (EC), alongside a receiver utilizing an envelope-detection demodulation technique for power reduction. The switched-capacitor power amplifier (SCPA) enables high output power through its high-efficiency characteristic, while a high-gain low-noise amplifier (LNA) ensures high-sensitivity reception. Compared with prior works, this transceiver achieves simultaneous high output power and high sensitivity within an ultra-low-power architecture, making it ideal for implantable bioelectronic applications. The proposed techniques reduce sleep-mode power consumption to 40 nW. The transmitter delivers 2.37-dBm output power with 8.2-mW consumption, and the receiver attains –64-dBm sensitivity with 200-µW consumption over a 10-meter wireless range.
Fully Homomorphic Encryption (FHE) enables computation on encrypted data without decryption, preserving data confidentiality. However, encrypting large datasets directly with FHE is often impractical due to substantial ciphertext expansion and communication overhead. Transciphering offers an efficient alternative by encrypting data with a lightweight symmetric cipher (e.g., AES) and then converting it into FHE ciphertext on the server. In this work, we propose MOTA, a framework for mapping and optimization of TFHE-friendly AES transciphering on near-memory FHE accelerators. We construct a compound gate library tailored for AES logic, designed for efficient mapping onto TFHE-compatible hardware implementations. We then optimize the circuit representation through an integer linear programming (ILP) formulation built upon the compound gate library. The resulting circuits are mapped to a representative class of programmable near-memory ASIC accelerators, enabling efficient execution with reduced data movement and specialized TFHE control flow. Experimental results demonstrate that MOTA achieves significant improvements in evaluation latency over conventional TFHE-friendly AES designs.
Large language models (LLMs) demand high-bandwidth and low latency on-chip communication fabrics. This paper presents a hierarchical mesh-of-trees (MoT) network-on-chip (NoC) based on blending mesh and tree topologies, and a corresponding simulation framework to optimize the LLM workload deployment. Our topology-mapping co-design framework models a hierarchical MoT NoC system and provides integrated cost estimation, mapping optimization, and utilization analysis. Evaluation results demonstrate improved network utilization and performance of LLM inference compared to the conventional flat NoC system. We conduct design space explorations across key design aspects—mapping strategy, cluster size, and LLM dimensions—to reveal design trade-offs and extensive insights.
This paper presents a 2.86–3.2 GHz digital fractional-N frequency-modulated continuous-wave (FMCW) chirp synthesizer employing a continuous-time bandpass delta-sigma time-to-digital converter (CT-BP∆Σ-TDC), which serves as the phase detector. The proposed architecture enables wide loop bandwidth operation for fast chirp generation while simultaneously maintaining low in-band phase noise, thus addressing critical challenges in modern radar and sensing applications. The synthesizer integrates several key components: a 2 GHz voltage-controlled oscillator (VCO); a multi-phase divider with phase interpolation for fine fractional frequency resolution; a high-order BP∆Σ-TDC sampled at the reference frequency with digital down-conversion to baseband; a digital loop filter; and on-chip chirp control circuitry. To overcome the fundamental loop-bandwidth limitation on achievable chirp slope, this work implements two-point modulation by combining N-path and VCO-path modulation with predistortion compensation based on a comprehensive VCO nonlinearity characterization. The 180 nm CMOS prototype achieves −120 dBc/Hz phase noise at 1 MHz offset (normalized PN: −256 dBc/Hz), a 0.6-1 MHz loop bandwidth, 2-5 MHz/µs chirp slope with a 100 kHz RMS frequency error, and −50 dBc reference spurs using phase-selection dither, while consuming 10 mW in a 0.05 mm2 area. Compared to PFD/CP-based PLLs, the CT-BP∆Σ-TDC provides superior near-DC noise suppression, reduced delay-mismatch sensitivity, an extended phase detection range, and improved chirp linearity through time-scheduled loop bandwidth control without compromising stability.
Hardware Trojans are malicious design modifications to integrated circuit (IC) designs, which pose severe threats to hardware security and trust. This work proposes a novel hardware Trojan detection method at gate level by exploring structural and behavioral features and training a machine learning model for node classification. The gate-level netlist is converted into a directed graph to extract structural features for each node. A random forest algorithm is then employed to analyze feature importance, providing explainable insights into the most influential features. In addition, we transform the netlist to bench format and extract three behavioral features from the perspective of controllability and observability. A neural network model with optimized class-balanced focal loss is trained for classifying circuit nodes and identifying Trojan-infected ones. Experiments using 80 hardware Trojan benchmarks from Trust-Hub and ATTRITION show that the proposed method can successfully pinpoint Trojan-infected nodes with true positive rate (TPR), true negative rate (TNR), accuracy, and area under the ROC curve (AUC) of 99.46%, 96.56%, 96.57%, and 98.01% respectively on average.
In recent years, deep learning has shown remarkable success in computer vision, inspiring its application to video coding. Neural network-based tools have demonstrated significant potential for enhancing compression efficiency. This paper presents a hybrid video coding framework that seamlessly integrates neural network-based modules into the conventional coding architecture. A Neural network-based Virtual Reference Frame generation network (NNVRF) is proposed to improve inter prediction by modeling both local and global spatiotemporal contexts, enhancing the quality of reference frames for motion compensation. In addition, a Multi-scale Transformer-based in-loop filter (MTILF) is designed with a hierarchical feature reconstruction backbone that captures cross-scale details while reducing computational complexity. Experimental results show that, under the Random Access configuration, NNVRF and MTILF achieve BD-rate reductions of 6.50% and 9.14% over the VTM-11.0 anchor for the Y component, respectively. When both tools are combined, the framework achieves overall BD-rate savings of 11.87%, 25.51%, and 24.62% for the Y, Cb, and Cr components.
The rising demand for multiplexed biomarker analysis in complex disease diagnostics, such as cancer, places a premium on biosensing technologies that can process multiple biochemical information with minimal power and footprint. Current systems, however, rely on complex analog front ends that make complex signal interpretation, increase energy consumption, and limit miniaturization. In this work, we overcome these limitations with a novel circuit based on nine triple-independent-gate reconfigurable field-effect transistors (RFETs). This circuit processes three analog inputs from a biotransducer, performing, if needed, in total up to eleven combinations of logic operations (showcased four in this work) to enable integrated in-sensor computing and multiplexing. The resulting output provides a direct digital correlation with pathological conditions, offering a clear pathway for therapeutic decision-making. We validated four core logic functions through in-silico simulations using models from Global TCAD Solutions, confirming the circuit’s operational principle.
This paper presents a high-speed, area-efficient adder design based on hybrid Single-Electron Transistor and MOS (SET-MOS) architectures. By utilizing the Coulomb oscillation characteristics of SETs, an integrated multi-input digital logic (a.k.a. Coulomb gate) is proposed to perform addition operations with significantly reduced area cost and improved area-delay product. In particular, we focus on design of a 2-bit adder which is implemented using only six transistors and three inverters, compared favorably with conventional CMOS counterparts. The proposed Coulomb gates are further extended to a 16-bit adder design with 70% reduction in transistor count and nearly 8% improvement in area-delay product compared to the best existing adders. This SET-MOS based approach offers a scalable and promising solution for arithmetic circuits that are widely used in IoT, edge computing, and biomedical systems.
The asymmetric single-pole-double-throw (SPDT) switch is a popular component in time-division duplex (TDD) RF front-end transceivers. In the conventional reflected-type configurations, potential internal reflection may be an issue when switching between the transmitting (Tx) and the receiving (Rx) modes, due to the fact that the Tx power amplifier is connected to the highly mismatched load during Rx operation. In this paper, the high power absorptive-type asymmetric SPDT switch is thus developed for 5G new-radio (NR) frequency range 2 (FR2) n257 band applications. Implemented in the 0.15-μm GaAs pseudomorphic high-electron-mobility transistor (pHEMT) technology, the experimental results demonstrated an insertion loss of less than 3.4/1.8 dB, an isolation of better than 17.9/18.1 dB, and an input 0.1-dB compression point (P0.1dB) of 30.0/22.0 dBm from 24-30 GHz while operating in Tx/Rx mode. Compared to the conventional asymmetric configurations, the proposed one offered a better isolation with lower insertion loss in the Rx mode.
This brief presents a ternary Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) aimed at reducing the power and area overheads while achieving speed improvement. The proposed ternary ADC is compatible with different DAC switching techniques. With the same switching techniques, the proposed ternary ADC reduces the DAC switching power consumption by 50% and the area by 66%, while achieving a 1.5x improvement in quantization speed compared to prior designs. The proposed ADC is simulated in a 40-nm CMOS technology with sampling rate of 1-GS/s and resolution of 6-bit. The simulation results achieve a 5.97 effective number of bits (ENOBs) with about 0.97-mW power consumption resulting in a FoM of 15.47fJ/conversion-step.
Federated learning with LoRA is widely used for parameter-efficient fine-tuning of large language models. To address system heterogeneity, current approaches typically assign varying LoRA ranks to clients with different resources. However, these heterogeneous methods suffer from feature dilution and high communication overhead. Furthermore, they often overlook the inconsistent update directions caused by Non-IID data. To overcome these limitations, we propose a simple yet effective federated heterogeneous LoRA approach. Our method treats the LoRA’s A matrix as a fixed orthogonal encoder to pre-align low-rank subspaces. Clients exclusively learn the decoder matrix B, which enables efficient dimensionality aggregation. Experimental results demonstrate that our method significantly outperforms state-of-the-art approaches in both convergence speed and communication efficiency.
