The commonly used deposition technology for solder bumps (evaporation or electroplating) requires thin-film processing. The compatibility of the solder-wettable metallizations does not allow the use of the same production equipment as installed in the wafer-fabrication facility. In this study, a maskless bump process is described. Here, solder droplets are ejected from a capillary and impinge on a wettable bond-pad metallizations of electroless-deposited Ni/P-Au. Droplets impinging on rough surface layer often bounce away. It is shown that this roughness layer is mainly determined by the Zn nucleation on the bond-pad metallizations. Nucleation conditions are optimized to deposit only small particles of the same size. The volume of the droplets depends on the product of pulse amplitude and pulse length. Degradation of the interconnection between the piezoelectric actuator and the glass capillary requires a larger pulse amplitude for stable jetting behavior. In addition, it is found that every first droplet on a new position is larger than all other droplets ejected directly thereafter. The diameter distribution of the latter are within the requirements for the final bump. The quality of the solder-jetted bump is studied by several reliability tests after flip-chip assembly on printed wiring boards (PWB's). In combination with underfill, the reliability of solder-jetted bumps are comparable with electroplated bumps.

For hand-held communication products, like the DECT telephone system, flip-chip on board offers minimization of both the package size and the occupied area on the boards. As a result of the reduction in interconnection lengths, the self-inductance is reduced. For high volume production, the compatibility of the flip-chip mounting technique with standard surface mount technology (SMT) reflow is essential. During reflow, the eutectic PbSn bump wets along the copper track, so the stand-off between integrated circuits (IC's) and the board is accurately defined by the layout of the board and the dimensions of the bump. The eutectic PbSn flip-chip processing is evaluated by impedance and cross-talk measurements, and in several reliability tests. For the electrical measurements, a zero-IF front-end IC is used. Wide-band measurements of the input impedance showed that the residual parasitics associated with the eutectic PbSn bumps are negligible compared with the parameters of the internal IC components. To accommodate the residual stresses from differences in coefficient of thermal expansion (CTE), the gap between the IC and the substrate is underfilled. This underfill material marginally affects the electrical behavior of the IC at frequencies up to a few GHz. As expected, a slight increase in the residual capacitance is observed. The effect of the underfill is studied by both temperature cycle and shock tests; cumulative failure distributions have been plotted. Results show that the adhesion properties and flow characteristics of the underfill material are the dominating factors for the number of cycles to failure. By selecting the proper underfill and curing conditions, the eutectic PbSn flip-chip construction can meet the test requirements for consumer communication products

Tape automated bonding (TAB) is a technique which is characterized by a small lead pitch, a small size, and a good high frequency behavior. To bond the inner leads of the TAB foil on the straight wall bumps on the integrated circuit (IC), thermocompression gang bonding is usually applied. If simple thin silicon nitride passivation layers are used, cracks are often observed in the sputtered TiW barrier layer (beneath the bump) and in the passivation layer of the IC. A theoretical model has been used to describe the deformation of the bump-lead structure. Comparison of this model with experimental results of the cracking behavior shows that both stress and strain at the bond pad-bump interface exceed the critical values for cracking. Plastic deformation at the bondpad is avoided if a two layer Ni-Au bump structure is used. While the plastic deformation required at the bond interface is kept constant, nickel layers with a thickness of at least 10 /spl mu/m are required to avoid even the smallest cracks. If the gold layer thickness is at least 15 /spl mu/m, the resulting bond strength is comparable with that of standard gold bumps. Deformation of the leads is restricted within acceptable limits, and the long-term reliability is not affected. Accelerated testing has been performed by high temperature storage, pressure cooker and air-to-air temperature shock testing.< >

For the DECT telephone system, a zero-IF front-end Integrated Circuit (UAA2078) has been designed in Philips' high speed QUBIC BiCMOS process. This IC contains all RF circuits required to directly down-convert the RF signal to the IF frequency around zero. At these high frequencies (1.8 GHz), it is advantageous to use flip-chip as mounting technique. Wide-band measurements of the input impedance showed that the residual parasitics associated with the eutectic solder bumps are negligible compared with the parameters of the internal IC components. To accomodate the residual stresses from differences in CTE, the gap between the IC and the substrate is underfilled. This underfill material does not affect chip behaviour too much at frequencies up to a few GHz. To study its mechanical behaviour, cumulative failure distributions have been investigated. The effect of the underfilling is studied by temperature shock-testing. From testing different types of underfill, it appears that the adhesion properties and flow characteristics of the underfill material are the dominating factors for the number of cycles to failure.

Flip-chip bonding, with an AuSn metallization system, has been successfully introduced for the mounting of integrated circuits (IC's) on flexible polyimide prints. Since in most consumer electronics, and more specifically for hearing instruments, the usable volume is decreasing very rapidly, maximum miniaturization is achieved by using flip-chips. In order to avoid open circuits during reflow soldering of all other components, a high melting soldering process is required for the bonding of the IC's. An additional advantage of the AuSn process is that the bumps do not completely melt, and a certain stand-off height is guaranteed. The bumps are deposited on top of the band pads and are bonded to copper tracks on a polyimide foil. The required tin is either deposited on the bump or on the copper tracks. Both AuSn soldering processes are performed by using pulsed heat thermode (gang) bonding. It has been found that the quality of the bonds depends on the microstructure formed in the bonding region. Energy dispersed X-ray analysis (EDX) measurements indicate that eutectic (80/20) Au-Sn or /spl xi/' phases are required for good quality bonds. To obtain these phases, the temperature at the interface and the initial amount of tin are optimized. As a consequence of a large thermal mismatch and a small stand-off height of the IC, the number of cycles to failure during temperature shock experiments is limited. The results are remarkably improved (by a factor of 20) by using an epoxy-based underfill material.< >

The Tape Automated Bonding (TAB) technique is characterized by a small lead pitch, a small size and a good high frequency behaviour. Usually thermocompression gang bonding on straight wall bumps is applied for the inner lead bonding of the integrated circuit to the flying leads of the TAB-foil. As a consequence of this process, cracks are often observed in the sputtered TiW barrier layer (beneath the bump) and in the passivation layer of the integrated circuit. A theoretical model has been used to describe the deformation of the bump-lead structure. Comparison of this model with experimental results of the cracking behaviour, shows that both stress and strain at the bondpad-bump interface exceed the critical values for cracking. Plastic deformation at the bondpad is almost avoided if a two layer Ni-Au bump structure is used. While the plastic deformation required at the bond interface is kept constant, Ni layers with a thickness of at least 10 μm are required to avoid even the smallest cracks. The resulting bond strength is comparable with that of standard Au bumps if the Au layer thickness is at least 15 μm. Then deformation of the leads is restricted within acceptable limits, and the long term reliability is not affected. Accelerated testing has been performed by high temperature storage, pressure cooker and air to air temperature shock testing

Tape automated bonding (TAB) is an interconnection technique for integrated circuits (ICs) with a small lead pitch and a thin assembly thickness. During inner lead bonding the flying (Au plated Cu) leads of the TAB foil are connected to the Au bumps on the bondpads of an IC. The Au bumps are deposited in the openings of a thick Novolac based resist layer by electroplating. The resist is coated on a sputtered TiW‐Au metallisation; TiW is the barrier layer between Au bump and Al bondpad. Bonding of the leads to the Au bumps requires substantial plastic deformation of the bump and lead. As a result of this deformation, the TiW barrier layer underneath the bump may crack easily. A theoretical model has been used to describe the occurrence of these cracks. This theoretical model is compared with experimental results of deformation and cracking behaviour by visual inspection of the TiW barrier and the etched cross‐sections. Separate (single point) and simultaneous (gang) bonding techniques, different gold plating baths and TAB tapes are used to study the cracking behaviour.

For Tape Automated Bonding (TAB) bumps are used for interconnecting the bondpads to the flying leads on a foil carrier. A sputtered barrier layer of TiW is present between the Al bondpads and the straight wall gold bumps, The electroplating process for bump deposition and the inner lead banding of the bumps is described for both Sulphitic and cyanic based gold baths. The hardness of the different deposited bumps is also measured after annealing. Auger Electron Spectroscopy was performed to study the diffusion through the TiW barrier layer, Visual inspection of the TiW barrier layer showed the relationship between bump hardness and the inner lead bonding conditions. The goal of this study is to acquire information on the influence of the hardness on the inner lead bonding process. The results presented so far are part of a larger TAB study, in which the hardness is only one of the parameters.