Purpose This study aims to investigate the multiphysics dynamic response of a resonant beam with an insulating substrate under electron irradiation. The focus is on revealing the electromechanical coupling effects between charge accumulation, structural deformation and the device’s micromechanical properties induced by electron beam irradiation, addressing critical reliability gaps in aerospace applications. Design/methodology/approach This paper establishes a Geant4-COMSOL coupling framework to simulate the response of silicon-based microelectromechanical system (MEMS) accelerometer structures under electron beam irradiation of 10–50 keV. Geant4 calculates spatial energy deposition, which COMSOL uses for multiphysics analysis. The authors evaluated varying beam energies (10–50 keV) and substrate materials, validating their predictive models with in situ scanning electron microscopy (SEM). Findings Ionization-induced charge accumulation and transient discharge within the SiO2 substrate drive the resonant beam’s nonlinear periodic oscillations. With increasing energy, structural displacement exhibits a nonmonotonic “decrease–increase–decrease” trend, while oscillation periods shorten. Comparisons with Si substrates confirm the SiO2 insulator’s decisive role in this response. Originality/value Combining in situSEM with cosimulation, this paper unveils the charge-induced discharge mechanisms causing nonlinear MEMS oscillations. These insights offer a crucial theoretical foundation for developing highly reliable, radiation-hardened microsystems for extreme space environments.
Purpose This study aims to realize large-scale and high-density manufacturing of conformal electronic devices by proposing a polydimethylsiloxane (PDMS)-based flexible packaging method via a 12-inch wafer-level redistribution-layer-first (RDL-first) process. Design/methodology/approach PDMS is used as the substrate to fabricate a conformal prototype, owing to its excellent processability, high flexibility and low cost. Electrical simulations show the series resistance and inductance of the daisy-chain structure. Mechanical simulations predict the stress distribution of the packaged structure under a 73.9 mm curvature radius, verifying its mechanical safety when embedded in a cranial mold. Experiments elaborate the process flow, mainly including temporary carrier preparation, RDL layer fabrication, chip flip-bonding and PDMS molding, successfully demonstrating a primary intelligent cranial prototype for signal processing and transceiving. Findings Mechanical simulations reveal that the maximum stress in the prototype when conformal to the cranial mold is 894.16?MPa with a PDMS thickness of 0.16 cm. The simulations also find that increasing PDMS thickness and reducing silicon thickness effectively lowers the maximum von Mises stress. A radio frequency (RF) signal processing prototype is precisely fabricated, containing four dies packaged in a dimension of 30 × 31.5 × 1.6 mm. It shows good flexibility with a minimum bending radius of 43.50 mm. The electrical test results demonstrate high consistency with the simulation results. Originality/value This work provides a processable, low-cost and high-efficiency packaging strategy for conformal electronics. PDMS encapsulation and 12-inch RDL-first wafer-level packaging process are combined. It may provide new strategies to wafer-level packaging technology in flexible applications.
Purpose While wide-bandgap (WBG) systems have been increasingly adopted in high-frequency, high-power, and high-temperature applications, efficient electrostatic management in compact devices continues to pose a challenge. There are few systematic investigations of compact electrostatic shielding in WBG platforms, despite research on material characteristics, device packaging, and two-dimensional material integration. Accordingly, this review aims to systematically evaluate recent advances in compact electrostatic shielding devices for WBG systems, with a particular focus on materials, fabrication strategies, and programmable microcontroller-based control approaches for real-time shielding optimization. Design/methodology/approach This review systematically synthesizes recent advances by integrating three key perspectives: (i) state-of-the-art shielding materials, (ii) fabrication strategies, and (iii) programmable microcontroller-based adaptive control frameworks for electrostatic field optimization. The methodology is based on a comparative literature analysis of electrostatic shielding mechanisms across heterogeneous systems, focusing on charge regulation and field redistribution under high-frequency, high-density conditions while enabling comparison of microcontroller-based enabling technologies and shielding strategies through their functional roles and performance metrics. Findings Key findings indicate that microcontroller-driven feedback, in conjunction with nanocomposites, MXenes, and multilayer coatings, can significantly enhance electrostatic protection while reducing footprint and cost. Compact electrostatic shielding approaches achieve moderate to high efficiency (0.49 s decay to 99.9% collection) with low-to-moderate footprint, weight, and dynamic adaptability, underscoring trade-offs in high-speed WBG systems. Additionally, integration challenges such as spatial restrictions, switching oscillations, and charge accumulation are addressed. Originality/value This review provides a strategic roadmap for more dependable next-generation WBG power electronics by combining advanced materials with adaptive control strategies to enable durable, compact, and adaptable electrostatic shielding solutions.
Purpose The purpose of this paper is to investigate the unique dielectrophoretic crossover frequency (f_x0) responses for real-time identification of six ESKAPE pathogens, Enterococcus faecium (EF), Staphylococcus aureus (SA), Klebsiella pneumoniae (KP), Acinetobacter baumannii (AB), Pseudomonas aeruginosa (PA) and Enterobacter aerogenes (EA) in the frequency range of kHz to MHz using an AC field. Design/methodology/approach The 2-shell model approach is employed using My DEP and COMSOL Multiphysics simulations to compute the proper dielectric modeling of ESKAPE pathogens. Dielectric modeling of ESKAPE pathogens is validated by dielectrophoresis (DEP) experiments in the range 100 kHz to 15 MHz at a fixed 6 Vpp. A unique crossover frequency (f_x0) is observed for each ESKAPE pathogen due to the differences in their morphological and electrical properties. Findings The ESKAPE pathogens have crossover frequencies of 11–11.2 MHz (EF), 6–6.05 MHz (SA), 7–7.10 MHz (KP), 6.1–6.15 MHz (AB), 10–10.06 MHz (PA) and 9–9.10 MHz (EA), respectively. The observed crossover frequency agrees with the 2-shell structure model of ESKAPE pathogens. Identification of ESKAPE based on their electrical response enables real-time detection in medical diagnosis and waterborne pathogen detection. Originality/value The application of input frequencies ranging from 100 kHz to 15 MHz at a constant 6 Vpp generated distinct frequency-response profiles for each ESKAPE pathogen, which can be used for ESKAPE pathogen detection in various biomedical applications.
Purpose This study proposes a fully differential, low-power, low-noise amplifier (LNA) with a 2nd-order Gm-C low-pass filter (LPF) for portable electroencephalogram (EEG) systems. The purpose of this study is to achieve an optimal noise-power tradeoff simultaneously minimizing input-referred noise (IRN) and power consumption. The study examines the impact of the proposed circuit design on the key parameters of EEG acquisition systems, particularly with regard to noise reduction and the overall system performance of an EEG system. Design/methodology/approach The research methodology combines both theoretical analysis and postlayout simulations using 0.18-µm CMOS technology to design and evaluate the proposed LNA architecture. The LNA incorporates a fully differential chopper-stabilized recycling double-folded cascode (FDCRDFC) amplifier and a 2nd-order Gm-C LPF. Its performance is benchmarked against conventional fully differential folded cascode amplifiers to highlight gains in noise reduction and power consumption. Findings The proposed LNA achieves a significantly reduced IRN of 0.62 µVrms over 0.1–100 Hz while consuming only 0.327 µW. The architecture has a mid-band gain of 64 dB and a bandwidth of 0.1–168 Hz, making it well-suited for portable EEG applications. The effective size of the proposed amplifier, including pads, is 560 × 560 µm2. Research limitations/implications This study focuses on the amplifier’s design and its impact on noise reduction and power consumption. Further studies could explore the integration of multiple channels in high-density EEG arrays or active ripple suppression techniques using a chopper or tunable filtering for multimodal bio-signal acquisition. Practical implications The significantly lower noise floor achieved by the proposed LNA enhances the signal quality in EEG acquisition systems, enabling more reliable real-time monitoring and improved accuracy in brain-health diagnostics. Originality/value The principal originality of this study compared to traditional approaches, lies in the co-optimized integration of the three key techniques: a recycling double-folded cascode (RDFC) amplifier for enhanced gain-efficiency, an NMOS-based chopper modulator for 1/f noise cancelation and a weak-inversion Gm-C filter for ripple suppression. This synergistic approach achieves an exceptional noise-power tradeoff, which is the critical benchmark for next-generation portable EEG acquisition.
Purpose This paper aims to critically examine the paradigm shift required to sustain wire bonding as a premier interconnection technology for next-generation semiconductor packaging. It moves beyond traditional empirical assessment to articulate a science-governed framework integrating advanced metallization, intelligent process control and nanoscale characterization, addressing the reliability challenges of wide bandgap (WBG) semiconductors, fine-pitch miniaturization (<40 µm) and harsh environment applications. Design/methodology/approach This critical synthesis review combines a systematic literature search (2020–2025) with a narrative, perspective-driven analysis. It synthesizes peer-reviewed literature to construct a comparative analysis of emerging wire/pad systems such as Ag alloys, Pd-coated Cu (PCC) and High-Entropy Alloys (HEAs) as well as their failure physics. It evaluates the transition from Design of Experiments to machine learning (ML)-driven adaptive control and quantifies the role of nanoindentation. Three comparative tables synthesize the analytical framework. Findings Key original syntheses include Pd as a tuneable kinetic moderator: Pd-coated Cu (PCC) reliability is directly controllable via Pd-layer thickness (80–120 nm), with thicker Pd (120 nm) reducing the Cu-Ag effective diffusion coefficient to 40%. Ag-alloy qualification: Ag96Pd3.5 bonding, optimized via Response Surface Methodology, offers a cost-effective method, though an industrial breakthrough requires migration to adaptive control architectures. Sensor-less intelligence: ML models using existing machine data achieve quantitative shear force prediction (R2 > 0.89), demonstrating that zero-defect production data is already generated but discarded. Nanoscale metrology: Creep property heterogeneity, rather than absolute hardness, correlates directly with reliability outcomes. Research limitations/implications This high-level synthesis identifies three critical research gaps: integration of HEA diffusion barriers with wire bonding metallization; transfer learning methodologies for ML models across wire diameters; and the “Green Paradox”, the trade-off between halogen-free mold compounds and increased thermomechanical stress on fine-pitch bonds. Originality/value This review offers a consolidated critical framework demonstrating wire bonding’s transition from an empirical “set-and-forget” process to a “cyber-physical-metallurgical” system. It provides original comparative analysis, author-constructed conceptual figures and explicit positions on contested technical debates, establishing that digital twins, diffusion barrier engineering and nanoscale metrology are current industrial necessities for supply chain resilience in automotive and power electronics.
Purpose This study aims to investigate the design, fabrication and characterisation of self-powered flexible pressure sensors based on zinc oxide (ZnO) nanorod arrays embedded in a poly(vinylidene fluoride) (PVDF) piezoelectric matrix, targeting continuous health monitoring and human-machine interface applications.Design/methodology/approach Vertically aligned ZnO nanorods were synthesised via low-temperature hydrothermal growth and embedded in an electrospun PVDF nanofibre matrix. Strain engineering was applied by controlling nanorod aspect ratio (diameter 80-250 nm; length 1.2-4.5 & micro;m) and nanocomposite thickness (20-80 & micro;m). Structural and electromechanical properties were characterised using X-ray diffraction, field-emission scanning electron microscopy, transmission electron microscopy, Raman spectroscopy and Fourier-transform infra-red spectroscopy. Output voltage, current density and sensitivity were measured under cyclic compressive loads from 0.1 to 500 kPa.Findings The optimised composite (aspect ratio 18:1, thickness 45 & micro;m) delivered an open-circuit voltage of 32.4V, short-circuit current density of 8.7 & micro;A cm & sup2; and peak power density of 28.6 & micro;W cm & sup2; at 50 kPa. Sensitivity reached 6.23 mV kPa & sup1; below 10 kPa, with a linear range of 0.1-500 kPa, response time of 28 ms and 96.2% output retention over 50,000 cycles. Real-time wrist pulse, finger-bending and plantar pressure monitoring were demonstrated without external power.Practical implications The battery-free architecture and low-cost hydrothermal synthesis present a scalable pathway towards self-powered diagnostic wearables for clinical and consumer health monitoring.Originality/value A holistic strain-engineering strategy combining nanorod aspect ratio tuning and matrix porosity control simultaneously maximises piezoelectric output and mechanical compliance, exceeding the sensitivity and power density of previously reported single-filler piezoelectric wearable sensors.
Purpose This paper aims to design and analyze a novel, very high gain, fully differential operational amplifier (op-amp). The design also addresses mismatch-induced offset in high-gain amplifiers with a novel static offset compensation circuit.Design/methodology/approach The op-amp incorporates a two-stage architecture comprising a high-gain stage and a moderate gain buffer stage. The high-gain stage features an independently biased input stage followed by a gain boosted cascode stage. The independent bias architecture helps to minimize the bias limitations placed on the high-gain stage. A class AB-biased push-pull output stage delivers the rail-to-rail output voltage swing. A miller compensation network and common-mode feedback circuit are also included. The integrated offset compensation offers a simple yet effective strategy for handling offsets, using minimal additional resources. The op-amp was designed in a commercial 180 nm 5 V CMOS process and can drive large capacitive loads up to 80 pF.Findings This paper presents the detailed design, analysis and simulation results of the proposed amplifier. Simulations show that the open loop gain, unity gain bandwidth and the phase margin (PM) of the amplifier while driving an 80 pF load are around 122 dB, 4.6 MHz and 62, respectively. The op-amp operates across a wide temperature range of 0-100 degrees C.Originality/value The op-amp delivers stable performance and exceptionally high gain across varying temperature and process conditions. The design introduces additional improvements over conventional architectures, including the integration of an independent bias-gm stage and pseudo-differential gain boosting. The proposed offset compensation circuit corrects mismatch-induced offset, common in high gain amplifiers, with minimal design overhead. A comprehensive noise analysis and stability analysis of the designed amplifier is also presented.
Purpose With the high penetration of distributed generators and the integration of large-scale emerging power sources and loads such as electric vehicles, Hybrid Distribution Transformers (HDTS) offer significant advantages in terms of flexible regulation and power quality improvement. However, due to high operating loads and the complex electrical environments frequently encountered during operation, these devices are prone to various faults such as overheating and breakdown. Despite their critical role, research on the reliability of hybrid distribution transformers has been lacking in recent years, posing significant challenges to the safety assessment of system operation. To address this gap, this paper investigates the electro-thermal stresses on components within HDTs under common extreme fault conditions. By considering ambient temperature conditions and overall structural imbalances, a lifetime analysis of both components and the system is conducted. Design/methodology/approach This paper investigates the electro-thermal stress on various components within HDTs under common fault conditions. Findings A lifespan evaluation of both the components and the system is conducted, considering the temperature conditions in both coastal and inland regions. Originality/value This paper conducts a lifetime evaluation study of key components in HDTs.
Purpose Patients with diabetes are at risk of developing chronic wounds, which can take months or years to heal naturally. This study aims to present the in vitro characterization of a dielectrophoresis (DEP) ratchet microelectrode for electric-field-assisted cell positioning (i.e. alignment and accumulation within defined gaps) of human epidermal keratinocytes (HEK) to enhance epithelialization in chronic wound environments.Design/methodology/approach MyDEP and COMSOL Multiphysics 5.6 were used to validate the experimental results. The DEP microelectrode was designed using AutoCAD and fabricated using surface micromachining to produce 40 and 60 mu m ratchet microelectrodes. DEP experiments were performed by applying sinusoidal AC potentials of 8, 10 and 12 V PP to the fabricated microelectrodes over a frequency range of 100 kHz to 25 MHz. The motion analysis software DIPP-MotionV was used to track cell positioning and accumulation and estimate cell speed.Findings The DEP experimental results, including cell positioning velocity and DEP response, were validated and correlated with the finite element method (FEM) and MyDEP data. The study successfully achieved in vitro HEK cell positioning at a rate of 263.33 mu m/s at 5 MHz, 8 V PP using a 40 mu m ratchet microelectrode. Cell viability assessment further confirmed that HEK cells remain viable at 8 V PP, supporting its suitability as a biologically safe operating condition. Furthermore, the device performance was compared between 40 and 60 mu m ratchet microelectrodes for effective cell positioning within defined gaps, achieving an efficiency of approximately 83.67% to 95.05%.Originality/value The DEP-based approach for in vitro HEK cell positioning within defined gaps using a 40 & micro;m ratchet microelectrode demonstrates high efficiency, indicating its potential for enhancing wound epithelialization and enabling rapid chronic wound closure.
Purpose Prior 12T hybrid SRAM cells offer high stability but introduce practical limitations like high control overhead and complex layouts, hindering large-array integration. This paper aims to propose a novel 12T topology overcoming these VLSI challenges while delivering exceptionally fast read operations.Design/methodology/approach A novel 12T hybrid tunnel field-effect transistor (TFET)-fin field-effect transistor (FinFET) SRAM is proposed. Unlike prior work focused on N-TFET pull-down paths, it introduces an innovative stacked four-PTFET pull-up network. The cell is validated using 20 nm InAs TFET and predictive technology model for multi-gate FinFET in simulation.Findings The architecture eliminates column-based write-assist signals, significantly reduced control complexity, while stacked PTFETs enable area-efficient device overlapping. Leveraging FinFETs in a decoupled read path, the cell achieves an exceptional 24 ps read latency at 0.6 V - outperforming 8T_S and HF_10T cells by approximately 130 & times; and approximately 20 & times;, respectively. Additionally, it secures the highest HSNM and RSNM among evaluated topologies (11% RSNM gain over recent 12T designs) and reduces leakage power by three orders of magnitude compared to the reference O_7T cell by effectively eliminating TFET reverse-bias currents.Originality/value This work presents the first hybrid 12T topology that resolves critical control-overhead and layout limitations while simultaneously shattering the read-speed bottleneck of TFET-based memories.
Purpose This paper aims to present an innovative three-dimensional (3D) homogenization method for rectangular wire winding, aiming to enable fast and accurate thermal analysis, which is essential for the design and safety assessment of electrical coils. Design/methodology/approach The homogenization process begins by defining a periodic microscopic unit cell that represents the internal structure of the winding. The equivalent thermal resistance of the unit cell is calculated along three orthogonal axes, from which the effective thermal conductivity in each direction is derived. The effective thermal properties of the equivalent homogeneous and anisotropic material are determined to model the thermal behavior of the original cell. These properties are then used to model the thermal behavior of the entire winding. To validate the method, a thermal equivalent circuit (TEC) is developed and used to analyze the coil’s thermal performance. Findings The results of the thermal analysis based on the homogenized model closely match those from detailed simulations, confirming the reliability of the proposed approach. The TEC effectively captures the temperature distribution and accurately identifies the hotspot location in the winding. The study includes both copper and aluminum conductors, revealing that the conductor material does not alter the hotspot’s location. Research limitations/implications The model assumes constant input power by reducing the coil current in response to increased resistance due to temperature rise. This simplifies the analysis but may not account for all real-world operating conditions. Originality/value This study introduces a novel 3D homogenization technique for rectangular wire winding, coupled with a TEC model. The proposed method enables efficient and precise thermal analysis, offering significant benefits in identifying critical thermal points, particularly the hotspot, in coil designs.
Purpose This study aims to present the design and implementation of a Class-J CMOS power amplifier (PA) targeting Bluetooth Low Energy (BLE) applications, addressing the critical requirements of efficiency, linearity and compact integration for low-power wireless communication.Design/methodology/approach Fabricated in 180 nm CMOS process, the proposed PA integrates an analog pre-distortion (APD) stage to enhance linearity by introducing opposing third-order nonlinearities to those of the main amplifier. Class-J operation is achieved through harmonic tuning, and an active load in the APD eliminates bulky passive RF chokes, reducing chip area. The PA is optimized for 2.45 GHz operation and characterized through on-chip measurements to validate performance.Findings The measured results demonstrate a forward gain (S21) of 20.5 dB, with input/output return losses (S11/S22) of -20.6 dB and -19.9 dB, indicating good impedance matching. The PA achieves a saturated output power of 15 dBm and a peak power-added efficiency of 47%. Linearity is confirmed with a third-order output intercept point of 19.9 dBm at an output power of 6.1 dBm, along with suppressed third-order intermodulation distortion (IMD3). The amplifier maintains unconditional stability across 1 GHz to 5 GHz with a stability factor (Kf) greater than 1.Originality/value The proposed PA demonstrates that a compact and linear Class-J architecture with APD can be effectively implemented in standard CMOS technology, making it well-suited for BLE transmitters in IoT and wearable devices.
Purpose The purpose of this study is expected to cover the main issues in photovoltaic (PV) power systems, including efficiency degradation, intermittent voltage and frequency variations in microgrids, inverter inefficiency and cost-effectiveness limitations. It proposes a high-tech PV power generation and use system to enhance the efficiency, stability and economic value of PV systems. Design/methodology/approach The proposed system integrates a hybrid photovoltaic-thermal (PV/T) configuration, a novel fuzzy-modified coot optimization (F-MCO)-based maximum power point tracking (MPPT) controller and a deep reinforcement learning (DRL) model enhanced with elephant herding optimization (EHO) for grid-forming inverter control. The F-MCO MPPT continuously adapts to environmental variations to extract maximum power, while the DRL-EHO-based inverter ensures autonomous voltage and frequency regulation in islanded microgrid mode. The system is evaluated using key performance indicators, including inverter efficiency, voltage and frequency stability and overall cost-effectiveness. Findings The simulations indicate that the proposed system can increase power production by a large margin, provide stable voltages and frequencies across different loads and enhance inverter functionality. The approach also has high potential to lower operational costs and to expand the use of high-quality, low-cost PV power systems. It is necessary to mention that these performance claims are based on the MATLAB/Simulink simulation studies and reflect the theoretical maximum performance. Practical implementation might be influenced by unmodelled physical effects, non-ideal hardware, sensor noise, communication delays and manufacturing variation, which may reduce actual end performance relative to simulated performance. The next step in the work will be to use hardware-in-the-loop (HIL) prototyping and field pilot testing to confirm the simulation results under real operating conditions. Originality/value The study presents a novel F-MCO MPPT method with a DRL-EHO-assisted grid-forming inverter, as well as a hybrid PV/T system with dual energy output. This unified system can provide an innovative way to maximize electrical and thermal efficiency, improve inverter performance and lower operating costs simultaneously, thereby addressing constraints that have not been adequately addressed in earlier PV system research.
Purpose With the continuous increase in the power density of electronic devices, their risk of thermal failure has risen significantly, posing severe challenges to their reliability. Although microchannel cooling technology can effectively control device temperatures, the internal fin structures, while enhancing heat transfer, also introduce high flow resistance and pump power consumption, thereby constraining system energy efficiency and long-term operational reliability. This paper aims to achieve synergistic optimization of efficient heat dissipation and low flow power consumption through structural optimization design, thereby reducing device operating temperatures and comprehensively improving their operational reliability. Design/methodology/approach A multi-stage collaborative optimization strategy for cylindrical finned structures is proposed. First, the effects of different shapes of perforated structures on flow and heat transfer are investigated, and the cylindrical perforated fin with the best overall performance is selected. Subsequently, a through-flow channel is introduced, and a secondary optimization is implemented by incorporating an arc-shaped flow guide contour. The finite element multiphysics simulation method is used to systematically analyze the temperature distribution, flow characteristics and energy consumption performance of the optimized structure. The accuracy of the model is verified through grid independence analysis and comparison with results from existing literature. Findings The perforated structure can effectively eliminate large-scale vortices in the backflow region of the fins, significantly reducing flow resistance while substantially maintaining the heat dissipation capacity. The cylindrical perforated structure achieves a maximum pressure drop reduction of 31.3%, with a 26.2% decrease in pumping power. After further optimization, the pressure drop is reduced by an additional 15.8%, and the pumping power decreases by 16.9%. The system maintains low-temperature operation while significantly reducing energy consumption, which helps enhance the thermal management and long-term operational reliability of the device. Originality/value This study achieves efficient thermal control of microchannel cooling systems under low pressure drop through multi-stage structural optimization, providing new insights for the thermal reliability design of high-power electronic devices. This method effectively reduces energy consumption while enhancing heat dissipation efficiency, demonstrating both engineering applicability and potential for reliability improvement.
Purpose - This study aims to investigate the inertia and damping support mechanism of the cascaded H-bridge converter-based battery energy storage system (CHB-BESS). The research helps improve the support performance of the CHB-BESS on the power electronics-based power systems. Design/methodology/approach - The study designs a dual-mode virtual inertia and damping control scheme. The first mode is adopted under the inertia response period. The second mode is adopted under the primary frequency control period after the frequency nadir/zenith to help the frequency recovery. Comparative electromagnetic transient simulation and experiments are conducted. Findings - The results reveal that both maximum frequency deviation and steady deviation is reduced by the proposed scheme. Under the 0.03 p.u. load changes, the frequency deviation is reduced by up to 7.6%, and the time that the system frequency reaches the steady value can be reduced by about 1.7 s, and the steady state frequency deviation is reduced by about 8.8%. Originality/value - This study further explores the frequency of the CHB-BESS and provides a valuable solution to the power system frequency regulation.
PurposeThe surface tension of Sn-based lead-free solders plays a critical role in determining their service performance in electronic packaging. Traditional experimental measurements are constrained by high cost, complex procedures and large data variability, while conventional theoretical models cannot fully characterize the complex nonlinear relationships between surface tension and its influencing factors. This study aims to develop a machine learning-based prediction method for the surface tension of Sn-based lead-free solders, providing reliable support for alloy composition optimization and industrial application.Design/methodology/approachA data set containing 169 groups of experimentally measured surface tension values was established from published literature. After preprocessing, the data set showed no missing values or outliers despite relatively uneven distribution, indicating satisfactory integrity suitable for small-sample machine learning modeling. Three machine learning algorithms, random forest (RF), support vector regression (SVR) and neural network (NN) were adopted and compared for surface tension prediction. Furthermore, an integrated hybrid model combining the three algorithms was constructed. Model performance was evaluated using mean squared error, root mean squared error, mean absolute error, coefficient of determination (R & sup2;) and analysis of variance.FindingsAmong the individual models, RF outperformed both SVR and NN. The proposed integrated hybrid model achieved significantly improved prediction accuracy, with a coefficient of determination R & sup2; up to 0.9437. Feature importance analysis and Pearson correlation coefficient analysis revealed that atomic volume and alloy composition are the dominant factors affecting the surface tension of liquid solders. Meanwhile, synergistic effects, including temperature, composition interactions and the correlation between atomic volume and electron density, exert notable influences on surface tension. Additionally, a simple and practical prediction equation was derived for convenient estimation of the surface tension of Sn-based solders.Originality/valueThis study systematically investigates the machine learning-based prediction of surface tension for Sn-based lead-free solders, proposing effective prediction models and a practical empirical equation. It provides important theoretical guidance for the compositional design of lead-free solders and the optimization of soldering processes, thereby promoting the development and industrial application of high-performance lead-free solder materials.
PurposeThis study aims to understand the phenomenon of stress relaxation in the gate pin of press-pack IGBT devices due to the coupling effect of electrical, thermal and mechanical fields, gate pin stress relaxation life model based on multiphysics field simulation and the Arrhenius equation is established. Taking the press-pack IGBT single-chip device as the research object, the stress distribution of the gate pin of the press-pack device is analyzed through simulation. The stress relaxation experiment of the gate pin establishes the thimble stress relaxation life models under different temperatures, and the power cycling experiments of the press-pack device verify the accuracy of the life model.Design/methodology/approachFirst, the COMSOL simulation is used to establish a multiphysics field model of the press-pack IGBT device to simulate the internal stress distribution characteristics of the device. Second, the stress relaxation formula of gate pin is established through constant-temperature experiments to quantify cumulative fatigue damage, and gate pin stress relaxation life model is built based on the Arrhenius equation. Finally, power cycling experiments are conducted to obtain the variation law of the electrical and thermal characteristic parameters of the device during the stress relaxation process of gate pin and verify the accuracy of gate pin life model.FindingsThrough multiphysics field simulation and stress relaxation experiments, it is found that the load loss rate of gate pin has a linear relationship with the logarithm of time, and the stress relaxation rate of the gate thimble varies significantly under different temperatures. Gate pin shows cumulative fatigue damage; the case temperature of the thimble and the corresponding junction temperature of the chip both increase with the same trend in the power cycling experiment. By monitoring the case temperature of pin, the time when the load loss rate of the thimble decays to the threshold can be estimated in real time.Originality/valueThrough multiphysics field simulation and experimental verification, this study proposes a stress relaxation mechanism of the gate pin under the multiphysics field coupling effect in press-pack IGBT devices, as well as its impact on device reliability.
PurposeThe purpose of this paper is to develop a novel design method for reconfigurable liquid crystal holographic antennas (LC-HAs) to suppress electromagnetic (EM) leakage and mutual coupling between radio frequency (RF) channels.Design/methodology/approachThe antenna is composed of tunable liquid crystal (LC) radiators and the feeding waveguide, which are coupled to each other through air slots opened on the upper wall of the waveguide. The slow wave is realized by a broken nail structure mounted on the lower wall of the waveguide. Attributed to the ingenious multimode-resonant antenna element design, the extremely high amplitude tuning efficiency of the antenna element is achieved under the limited LC volume.FindingsAttributed to the ingenious multimode-resonant antenna element design, the extremely high amplitude tuning efficiency of the antenna element is achieved under the limited LC volume, which enables the proposed LC-HA to reach a scanning angle of -60 degrees to + 60 degrees, and the gains of 12.5 dB - 15 dB over the whole scanning angle. Holographic algorithm is used to realize beam scanning. Numerical simulation results are highly consistent with the preset angle of the algorithm, indicating that the working mechanism and design method of the proposed antenna are reasonable and proper. An antenna prototype is fabricated and measured. The experimental results are consistent with the simulation results.Originality/valueThis paper provides a novel design method for reconfigurable LC-HAs fed by a slow-wave rectangular waveguide, which has an advantage over existing microstrip-fed or gap-waveguide-fed LC-HAs in suppressing EM leakage and mutual coupling between RF channels.
