The development of superconducting quantum computing platforms faces considerable scaling challenges because individual signal lines are required to control each qubit. This wiring overhead is a result of the low level of integration between the control electronics at room temperature and the qubits operating at millikelvin temperatures. A promising alternative is to use cryogenic superconducting digital control electronics that coexist with qubits. Here we present an active quantum processor unit in which qubits and single-flux quantum control electronics are integrated into a single multi-chip module via flip-chip bonding. Our system uses digital demultiplexing to distribute control pulses to several qubits, thus breaking the linear scaling of control lines to the number of qubits. With this approach, we demonstrate single-qubit fidelities above 99% and up to 99.9%.

We implemented, optimized and fully tested over multiple runs a superconducting Josephson junction fabrication process tailored for the integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient single flux quantum (ERSFQ) circuits with the critical currents reduced by factor of ~10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 uA unit critical current fabricated with a 10 uA/um2 critical current density. In order to circumvent the substantial size increase of the SFQ circuit inductors, we employed a NbN high kinetic inductance layer (HKIL) with a 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with a 4.0 ohm/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 um height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive Process Control Monitor chip set.

We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm(2) fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab's 10-kA/cm(2) SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.

We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bidirectional SHIFT instruction of an 8-bit argument. It consists of a bidirectional triple-port shift register controlled by two (left and right) shift pulse generators asynchronously generating a set number of shift pulses. At first clock cycle, an 8-bit word is loaded into the binary shifter and a 3-bit shift argument is loaded into the desired shift-pulse generator. Next, the generator produces the required number of shift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set by the internal generator delay of ∼ 30 ps. These SFQ pulses are applied to the left (positive) or the right (negative) input of the binary shifter. Finally, after the shift operation is completed, the resulting 8-bit word goes to the parallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820 Josephson junctions, was simulated and optimized using PSCAN2. It was fabricated in MIT Lincoln Lab's 10-kA/cm2 SFQ5ee fabrication process with a high-kinetic inductance layer. We have successfully tested the binary shifter at both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shift arguments. A single shift operation on a single input word demonstrated operational margins of ±16% of the dc bias current. The correct functionality of the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern was observed within ±10% margins of the dc bias current. In this paper, we describe the design and present the test results for the ERSFQ 8-bit parallel binary shifter.

An approach for scalable quantum computing infrastructure based on the use of low-power digital superconducting single flux quantum (SFQ) circuits is described. Rather than replicating the room-temperature microwave control and measurement infrastructure solutions dominating the current systems, we use the inherent to superconducting technology methods - the use of SFQ pulses directly at the base temperature. For qubit control, we irradiate qubits with the coherent SFQ pulse sequences computed using optical control theory. For qubit measurement, Josephson photon counter performs projective quantum measurement, the result of which is converted to digital SFQ output. These operations are aided by a high-speed digital SFQ coprocessor located at higher temperature stage (e.g., 3 K) to process the measurement results and load new control sequences to 20 mK SFQ quantum-classical interface circuits.

As superconducting quantum processors increase in size and complexity, the scalability of standard techniques for qubit control and readout becomes a limiting factor. Replacing room temperature analog components with cryogenic digital components could allow for the realization of systems well beyond the current state-of-the-art qubit arrays with tens of qubits. The standard technique for performing a qubit measurement with heterodyne readout uses a quantum-limited cryogenic amplifier chain and requires bulky microwave components inside the refrigerator with multiple control lines and pump signals. Additionally, the result is only accessible in software at room temperature. An alternative method for measuring qubits involves mapping the qubit state onto the photon occupation in a microwave cavity, followed by subsequent photon detection using a Josephson photomultiplier (JPM). The JPM measures the qubit and stores the result in a classical circulating current. To make use of this result, we can leverage existing single flux quantum (SFQ) circuitry. An underdamped Josephson transmission line (JTL) can be coupled to the JPM and fluxons traveling along the JTL are accelerated or delayed, depending on the circulating current state of the JPM. This fluxon delay can then be converted to an SFQ logic signal resulting in a digital qubit readout with a proximal microfabricated device, paving the way for cryogenic digital feedback necessary for error-correcting codes.

Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a "feeding" JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm(2) fabrication processes and tested at low (similar to kHz) and high (similar to GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/-4% to over +/-19% when the Josephson junction count in the FJTL was increased to similar to 30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.

A focused ion beam was used to obtain cross-sectional specimens from both magnetic multilayer and Nb/Al-AlOx/Nb Josephson junction devices for characterization by scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX). Automated multivariate statistical analysis of the EDX spectral images produced chemically unique component images of individual layers within the multilayer structures. STEM imaging elucidated distinct variations in film morphology, interface quality, and/or etch artifacts that could be correlated to magnetic and/or electrical properties measured on the same devices.

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We present test results for parallel data communication ERSFQ circuits with clock recovery. We experimentally study on-chip and chip-to-chip parallel data communication circuits with 4-, 8- and 16-bit word lengths. The largest circuit is a 16-bit chip-to-chip communication test circuit embedded into a testbed with clock distributed over a combination of active and passive transmission lines with transmitter/receiver pairs, and is comprised of 3464 Josephson junctions in total. All ERSFQ circuits are fabricated using MITLL 10-kA/cm 2 SFQ5ee process. For the chip-to-chip communication experiment, a multi-chip module (MCM) is assembled using Hypres' MCM flip-chip bonding process which connected the MIT-LL-made flip-chip to the Hypres-made MCM carrier using 220 signal bumps with 50 um pitch. We experimentally confirmed correct functionality of 4-, 8- and 16-bit circuits and measured their current bias margins. For the 16- bit chip-to-chip communication circuit mounted to a MCM, we measured ±12% dc bias margins similar to the margins measured for the on-chip version of the same circuit. The MCM circuit is also evaluated at high clock speed generated by an external source, while the data words are changed at low speed. The correct functionality is observed without significant reduction in the bias margins using average-voltage test approach.

We report on the development of energy-efficient decoders for cryogenic random access memory and register file. To reduce the pitch, area, and energy, our decoder employs a scalable binary tree architecture. We implemented these decoders using ERSFQ logic controlled by magnetically coupled address lines. These lines are driven by energy-efficient drivers based on the current-stirring technique. A 4-to-16 version of the decoder was laid out and fabricated in HYPRES 6-layer 10 kA/cm(2) and MIT LL 8-layer 10 kA/cm(2) processes with 15 and 28 mu m decoder row pitch, respectively. The decoders were designed to have similar to 30 ps latency and dissipate similar to 40 aJ per clock. We experimentally confirmed the functionality of the circuits with +/- 8% dc bias margins and verified its operation up to 13 GHz clock.

We designed, fabricated, and demonstrated an energy-efficient ERSFQ 4-bit decoder. The first version of the decoder is designed and fabricated using HYPRES legacy 1.0-μm four-layer 4.5-kA/cm2 process. It occupies an area of 700 μm × 1800 μm, which is to be reduced to 160 μm × 400 μm once fabricated using HYPRES's RIPPLE-2 0.25-μm six-layer process. The decoder features ±13% dc bias current operating margins and below 70-aJ energy consumption per one address select operation. We report test results of the decoder and discuss its future implementation in cryogenic random access memory devices, including magnetic memory devices.

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.

We present the quasi-static and dynamic switching characteristics of orthogonal spin-transfer devices incorporating an out-of-plane magnetized polarizing layer and an in-plane magnetized spin valve device at cryogenic temperatures. Switching at 12 K between parallel and anti-parallel spin-valve states is investigated for slowly varied current as well as for current pulses with durations as short as 200 ps. We demonstrate 100% switching probability with current pulses 0.6 ns in duration. We also present a switching probability diagram that summarizes device switching operation under a variety of pulse durations, amplitudes, and polarities.

As a part of the 8-bit RSFQ processor datapath development, we have designed, fabricated, and experimentally demonstrated an 8×8-bit RSFQ multi-port register file. The register file provides input data operands and stores Arithmetic Logic Unit (ALU) results. It can perform two simultaneous non-destructive “read” operations and one “write” operation and is capable of storing eight 8-bit words. The distinct feature of the design is an extensive use of passive transmission lines (PTLs) for very complex interconnects inside the register file. The register file is designed for integration with recently demonstrated 20-GHz 8-bit RSFQ ALU. It is fabricated with the standard HYPRES's 1.0-um 4.5-kA/cm2 process. The circuit is placed on a 1 cm × 1 cm chip and consists of ~4,000 Josephson junctions.

We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.