We present the design, analysis, and real-time implementation of a distributed computation particle filter on a graphic processing unit (GPU) architecture that is especially suited for fast real-time control applications. The proposed filter architecture is composed of a number of local subfilters that can share limited information among each other via an arbitrarily chosen abstract connected communication topology. We develop a detailed implementation procedure for GPU architectures focusing on distributed resampling as a crucial step in our approach, and describe alternative methods in the literature. We analyze the role of the most important parameters such as the number of exchanged particles and the effect of the particle exchange topology. The significant speedup and increase in performance obtained with our framework with respect to both available GPU solutions and standard sequential CPU methods enable particle filter implementations in fast real-time feedback control systems. This is illustrated via experimental and simulation results using a real-time visual servoing problem of a robotic arm capable of running in closed loop with an update rate of 100 Hz, while performing particle filter calculations that involve over one million particles.

The particle filter is a Bayesian estimation technique based on Monte Carlo simulation. It is ideal for non-linear, nonGaussian dynamical systems with applications in many areas, such as computer vision, robotics, and econometrics. Practical use has so far been limited, because of steep computational requirements. In this study, we investigate how to design a particle filter framework for complex estimation problems using many-core architectures. We develop a robotic arm application as a highly flexible estimation problem to push estimation rates and accuracy to new levels. By varying filtering and model parameters, we evaluate our particle filter extensively and derive rules of thumb for good configurations. Using our robotic arm application, we achieve a few hundred state estimations per second with one million particles. With our framework, we make a significant step towards a wider adoption of particle filters and enable studies into filtering setups for even larger estimation problems.

The particle filter is a Bayesian estimation technique based on Monte Carlo simulation. The nonparametric nature of particle filters makes them ideal for non-linear, non-Gaussian dynamic systems. Particle filtering has many applications: in computer vision, robotics, and econometrics to name just a few. Although superior to Kalman filters, particle filters have higher computational requirements, which limits practical use in real-time applications. In this paper, we investigate how to design a particle filter framework for complex real-time estimation problems using modern many-core architectures. We develop a robotic arm application that serves as a highly flexible estimation problem to push estimation rates and accuracy to new levels. By varying different filter and model parameters, we derive rules of thumb for good filter configurations. We evaluate our particle filter with a comprehensive performance and correctness analysis. Our results significantly lower the development effort of particle filters for other real-time estimation problems. For the most demanding robotic arm configuration, we can process one million particles at an update rate of a few hundred state estimations per second. As such, we see our results as a step towards wider adoption of particle filters, and as a prerequisite to investigate larger filter setups for even more complex estimation problems.

When computer architects reinvented parallelism through multi‐core processors, application parallelization became a problem. Now that multi‐cores have penetrated from handhelds to supercomputers, parallelization becomes a large‐scale challenge. A lot of research is going into compiler improvements, language extensions, frameworks and application/platform case studies. Whereas fairly successful, these solutions are based on experimental tools, trial‐and‐error, and expert knowledge, and do not bring multi‐core programming into reach for the whole software industry. We believe that the challenge of “mass parallelization” must be tackled more systematically. Development begins at application specification and algorithm design, followed by application characterization with trade‐offs in parallelization strategies and data layouts. Only with a proper software design, implementation and optimization can start. In this article, we focus on quantitative application characterization for such a systematic approach. We introduce a set of metrics to characterize applications and show how they can be used. We present our interpretation of the results and suggest ways to use them to guide design decisions. We conclude that metrics can be used to understand applications and design decisions early on. Therefore, this characterization brings us closer to effective parallel applications development for multi‐core processors. Copyright © 2011 John Wiley & Sons, Ltd.

Memory architectures need to adapt in order for performance and scalability to be achieved in software for multicore systems. In this paper, we discuss the impact of techniques for scalable memory architectures, especially the use of multiple, non-cache-coherent memory spaces, on the implementation and performance of consumer software. Primarily, we report extensive real-world experience in this area gained by Codeplay Software Ltd., a software tools company working in the area of compilers for video games and GPU software. We discuss the solutions we use to handle variations in memory architecture in consumer software, and the impact such variations have on software development effort and, consequently, development cost. This paper introduces preliminary findings regarding impact on software, in advance of a larger-scale analysis planned over the next few years. The techniques discussed have been employed successfully in the development and optimisation of a shipping AAA cross-platform video game.

When computer architects re-invented parallelism through multi-core processors, application parallelization became mandatory. The challenge of “mass-parallelization” forced the software community to react quickly. Unfortunately, instead of tackling such a large-scale problem in a systematic way, we have rather experienced various random search, non-portable and non-reusable approaches. We believe that the way to effectively address the problem is to limit its scale by splitting the potentially infinite application space into a limited set of application classes. This idea is not entirely new, as a similarity-based taxonomy has been recently proposed. However, in this paper, we purpose a different approach that focuses on a mostly quantitative application characterization. We introduce a set of metrics to characterize applications and we show how they can be evaluated for three case-studies. Once a wide range of applications have been characterized, we can identify a limited number of application classes. Next, for these classes, dedicated programming tools can be used to write high-performance parallel software in a productive way.

When computer architects re-invented parallelism through multi-core processors, application parallelization became mandatory. The challenge of “mass-parallelization” forced the software community to react quickly. Unfortunately, instead of tackling such a large-scale problem in a systematic way, we have rather experienced various random search, non-portable and non-reusable approaches. We believe that the way to effectively address the problem is to limit its scale by splitting the potentially infinite application space into a limited set of application classes. This idea is not entirely new, as a similaritybased taxonomy has been recently proposed. However, in this paper, we purpose a different approach that focuses on a mostly quantitative application characterization. We introduce a set of metrics to characterize applications and we show how they can be evaluated for three case-studies. Once a wide range of applications have been characterized, we can identify a limited number of application classes. Next, for these classes, dedicated programming tools can be used to write high-performance parallel software in a productive way.

Computing many small 2D convolutions using FFTs is a basis for a large number of applications in many domains in science and engineering, among them electromagnetic diffraction modeling in physics. The GPU architecture seems to be a suitable architecture to accelerate these convolutions, but reaching high application performance requires substantial development time and non-portable optimizations. In this work, we present the techniques, performance results and considerations to accelerate small 2D convolutions using CUDA, and compare performance to a multi-threaded CPU implementation. To improve programmability and performance of applications that make heavy use of small convolutions, we argue that two improvements to software and hardware are needed: FFT libraries must be extended with a single convolution function and communication bandwidth between CPU and GPU needs to be drastically improved.

Multi-core platforms have proven themselves able to accelerate numerous HPC applications. But programming data-intensive applications on such platforms is a hard, and not yet solved, problem. Not only do modern processors favor compute-intensive code, they also have diverse architectures and incompatible programming models. And even after making a difficult platform choice, extensive programming effort must be invested with an uncertain performance outcome. By taking the plunge on an irregular, data-intensive application, we present an evaluation of three platform types, namely the generic multi-core CPU, the STI Cell/B.E., and the GPU. We evaluate these platforms in terms of application performance, programming effort and cost. Although we do not select a clear winner, we do provide a list of guidelines to assist in platform choice and development of similar data-intensive applications.

The performance potential of the Cell/B.E., as well as its availability, have attracted a lot of attention from various high-performance computing (HPC) fields. While computation intensive kernels proved to be exceptionally well suited for running on the Cell, irregular data-intensive applications are usually considered as poor matches. In this paper, we present our complete solution for enabling such a data-intensive application to run efficiently on the Cell/B.E. processor. Specifically, we target radioastronomy data gridding and degridding, two resembling imaging filters based on convolutional resampling. Our solution is based on building a high-level application model, used to evaluate parallelization alternatives. Next, we choose the one with the best performance potential, and we gradually exploit this potential by applying platform-specific and application-specific optimizations. After several iterations, our target application shows a speed-up factor between 10 and 20 on a dual-Cell blade when compared with the original application running on a commodity machine. Given these results, and based on our empirical observations, we are able to pinpoint a set of ten guidelines for parallelizing similar applications on the Cell/B.E. Finally, we conclude the Cell/B.E. can provide high performance for data-intensive applications at the price of increased programming efforts and with a significant aid from aggressive application-specific optimizations.

Now that large radiotelescopes like SKA, LOFAR, or ASKAP, become available in different parts of the world, radioastronomers foresee a vast increase in the amount of data to gather, store and process. To keep the processing time bounded, parallelization and execution on (massively) parallel machines are required for the commonly-used radioastronomy software kernels. In this paper, we analyze data gridding and degridding, a very time-consuming kernel of radioastronomy image synthesis. To tackle its its dynamic behavior, we devise and implement a parallelization strategy for the Cell/B.E. multi-core processor, offering a cost-efficient alternative compared to classical supercomputers. Our experiments show that the application running on one Cell/B.E. is more than 20 times faster than the original application running on a commodity machine. Based on scalability experiments, we estimate the hardware requirements for a realistic radio-telescope. We conclude that our parallelization solution exposes an efficient way to deal with dynamic data-intensive applications on heterogeneous multi-core processors.