The GR716B is a rad-hard and fault-tolerant mixed-signal microcontroller. The GR716B has been developed to provide high computational performance, support for advanced interfaces, several analog functions, possibilities to control switching power applications, and support functionality for supervision and control of SRAM FPGAs in space. The GR716B is currently in development and prototypes will be available in Q1 2024. This paper describes the overall functionality of the device and applications in which the device can be used to control advanced functions. The applications described are DC/DC converter control, motor control and magnetorquer driver control.

Aeroflex Gaisler has developed, under European Space Agency (ESA) contract 4000104519, a draft ECSS protocol for the transmission and synchronization of CCSDS Unsegmented Code (CUC) time in SpaceWire networks. The working name of the protocol is “Time Distribution Protocol”. Apart from transmission and synchronization of time across the SpaceWire network, the protocol also provides guidelines to achieve highly accurate time synchronization by mitigating jitter and latency affecting SpaceWire Time-Code transmission in a SpaceWire network. The protocol also provides guidelines for correcting clock drift appearing in local SpaceWire nodes. A prototype implementation of the protocol was performed and analyzed for intended functionality. The implementation of jitter and drift mitigation is based on a simple time interval measurement of incoming SpaceWire Time-Codes using local clock. Statistical information is gathered, which is then used to calculate an average correction value that is applied to modify a frequency synthesizer which provides inputs for the time generation. By controlling the frequency synthesizer the time is maintained stable without drift arising from oscillator or crystal used to generate the local clock. Distributed interrupts are used for latency measurement between two nodes in a SpaceWire network. Time-stamping of reception and transmission of distributed interrupts provides the values needed to calculate latency. The calculated latency value is used for correcting the time maintained in the system. By performing CCSDS Unsegmented Code (CUC) transmission and latency, jitter, drift mitigation a stable time keeping in a system is achieved.

The Purpose of this Master thesis is to integrate the Xilinx PCI-Express interface core to the GRLIB framework. Xilinx Spartan6 Endpoint block for PCI-EXPRESS is generated using Coregen and integrated with the GRLIB framework. The design accounts for crossing clock domains as it is inevitable in a system of chip design with multiple components running at different frequencies. The implementation satisfies the Specification provided by AMBA and PCI-EXPRESS. The performance and area requirement are taken into consideration and different forms of the design is implemented in order to address it. The communication between PC and GRLIB memory environment and the other way around is performed and verified. Simple C codes are developed in order to initiate transfers and also to verify the design. Debugging tools like GRMON, LSPCI and drivers provided by Xilinx are used for analysing and verifying the design. Using GRMON the PCI-EXPRESS debug environment could transfer data at the rate of 120 Mbits/second from PC to the memory of GRLIB. The complete design work was carried out at Aeroflex Gaisler AB.

Aeroflex Gaisler (SE) has together with Pender Electronic Design (CH) and Hirel Design (NL) has under DLR (D) contract and VEGA (D) management developed the Onboard Computer (OBC) engineering model (EM) for the MASCOT asteroid lander.