This work presents the radiation characterization of the COTS Myriad X Vision Processing Unit, from Intel Movidius, for proton- and heavy ion-induced Single Event Effects and Total Ionizing Dose. The component has already flown on different missions, and it continues to be considered in future ones. The results obtained show that the radiation performance of the device is aligned with the performance of other components manufactured in the 16nm FinFET technology. Potential use cases of Myriad X in space computing platforms are also discussed.

During the design phase of a fault-tolerant LEON4 quad-core processor ASIC for space applications, a Californium $252\left({}^{252} \text{Cf}\right)$ source was used to inject errors on the memory cells of a test vehicle to verify the error correction scheme embedded in the Level-1 (L1) and Level-2 (L2) cache of the processors. An issue, that could have caused a significant detrimental effect on the radiation performance of the processor, was identified, and delimited to the $\mathbf{L 2}$ cache. The ${}^{252} \mathbf{C f}$ source allowed the authors to do a quick validation of the $L 2$ cache, to test a software workaround and kick-off a new revision of the chip. Breaking tradition, the ${}^{252}$ Cf source was used as an alpha emitter instead of a heavy ion emitter. This work aims at showing that ${}^{252} \text{Cf}$ sources, long disused for SEE testing, may still be useful for the injection of SEUs in the memory cells of submicron ICs. Error maps generated with alpha particles are also compared against proton and heavy ion's induced error maps.

The GR765 is an octa-core system-on-chip that is currently in development and is being designed with high levels of radiation hardening and fault-tolerant features. This chip incorporates both the SPARC and RISC-V Instruction Set Architectures (ISA), providing users with the flexibility to choose the best architecture for their specific application requirements. The switching between the two ISAs is achieved through a bootstrap signal. The GR765 is designed with an advanced SoC architecture and a diverse set of peripherals, indicating its potential to serve as a robust and efficient computing platform.

This work presents the SEE characterization of the first Frontgrade Gaisler’s LEON5FT and NOEL-VFT implementation in a test chip built on STMicroelectronics’ 28nm FDSOI GEO P2 technology platform. Results show the effectiveness of processors’ fault tolerance in handling soft errors. All detected memory errors were successfully corrected without software interference.

The GR716 is a radiation hardened mixed-signal microcontroller with fault-tolerant features. It is available in two versions, the GR716A and the GR716B. The former has already been extensively tested for electrical and radiation performance, and flight parts are currently available. The latter, based on the GR716A design, is being developed to provide higher computational performance, support for more interfaces, enhanced analog functions, support for switching power applications, and functionality to support the use of commercial off the shelf (COTS) FPGAs in space. The GR716B is currently under development, with prototypes expected to be available in Q1 2024. This paper provides an overview of the architecture of both devices and focuses on the additional features and functionalities offered by the GR716B microcontroller.

The GR765 is a radiation-hardened octa-core fault-tolerant system-on-chip currently in development. This work presents the radiation evaluation of a test vehicle based on the same technology platform intended to be used in the GR765. Results show the effectiveness of the technology and processors' fault tolerance in handling soft errors.

The GR716B is a rad-hard and fault-tolerant mixed-signal microcontroller. The GR716B has been developed to provide high computational performance, support for advanced interfaces, several analog functions, possibilities to control switching power applications, and support functionality for supervision and control of SRAM FPGAs in space. The GR716B is currently in development and prototypes will be available in Q1 2024. This paper describes the overall functionality of the device and applications in which the device can be used to control advanced functions. The applications described are DC/DC converter control, motor control and magnetorquer driver control.

GR716A is a mixed-signal radiation-hardened Microcontroller built around a LEON3FT fault-tolerant processor developed by Frontgrade Gaisler. The development of the GR716A was initiated and funded by the European Space Agency within the Embedded Microcontroller for Space Applications activity. The GR716A is implemented using Imec's DARE180 radiation-hardened cell library in a 180 nm CMOS technology platform from UMC. This work presents the SEE characterization of the GR716A Microcontroller based on data collected from irradiation test campaigns performed by Frontgrade Gaisler. The results show an overall SEE error rate below 7.0x10-6 events/device/day for typical space orbits and a SEL immunity up to an LET of 125 MeV.cm 2 /mg,

The GR765 is a radiation-hardened system-on-chip planned to be the successor of the GR740 quad-core LEON4FT processor. The GR740 LEON4FT quad-core processor is the highest performing LEON-based component currently available for space applications and is being applied in various missions and spacecraft architectures. The GR765 architecture includes several improvements over the GR740, most notably the addition of the bootstrap option to select between the LEON5FT and NOEL-V FT high-performance processors that will further increase computational performance over the LEON4FT used in the GR740. The GR765 provides a low-threshold upgrade path for current GR740 users that need additional computational performance, improved power performance, or that would benefit from the extended functionality in the new architecture.

This work presents the SEE fault tolerance characterization of the NOEL-V FT RISC-V processor IP core combined with the GRSCRUB FPGA supervisor protection on a Xilinx Kintex UltraScale FPGA. Additionally, a distributed TMR synthesis strategy is applied to enhance the resilience of the system against SEE. Results from a proton beam irradiation show the efficiency of the NOEL-V fault tolerance features in correcting single errors and preventing error accumulation, the GRSCRUB’s advanced capability of error detection and correction, and the masking effects of the distributed TMR method.

The GR740, developed by Cobham Gaisler, is a radiation-hardened System-on-Chip that features a quad-core fault-tolerant LEON4 processor. The GR740 has been designated as the European Space Agency's “Next Generation Microprocessor.” The GR740 is implemented in the 65nm CMOS technology platform for space applications developed by STMicroelectronics. This work presents the Single Event Effect characterization of the GR740 flight silicon. The low rate of functional errors recorded in application-level testing under irradiation demonstrates the effectiveness of the radiation-hardening scheme selected for this device. Although an extensive number of radiation-induced events in the internal memory cells were recorded, all events were successfully mitigated and corrected. No evidence of error build-up was observed in the GR740.

The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade processors in the market; (2) access to an increasingly rich software ecosystem rather than sticking to the slowly fading SPARC and PowerPC-based ones; (3) freedom (or drastic reduction) of export and license restrictions imposed by commercial ISAs such as Arm; and (4) improved support for the design and validation of safety-related real-time applications, (5) being the platform with software qualified and hardware designed per established space industry standards. De-RISC partners have set up the different layers of the platform during the first phases of the project. However, they have recently boosted integration and assessment activities. This paper introduces the De-RISC space platform, presents recent progress such as enabling virtualization and software qualification, new MPSoC features, and use case deployment and evaluation, including a comparison against other commercial platforms. Finally, this paper introduces the ongoing activities that will lead to the hardware and fully qualified software platform at TRL8 on FPGA by September 2022.

This extended abstract describes the development of a RISC-V-based System-on-Chip design targeting space applications.

One of the traditional issues in space missions is the reliability of the electronic components on board spacecraft. There are numerous techniques to deal with this, from shielding and rad-hard fabrication to ad-hoc fault-tolerant designs. Although many of these solutions have been extensively studied, the recent utilization of FPGAs as the target architecture for many electronic components has opened new possibilities, partly due to the distinct nature of these devices. In this study, we performed fault injection experiments to determine if a RISC-V soft processor implemented in an FPGA could be used as an onboard computer for space applications, and how the specific nature of FPGAs needs to be tackled differently from how ASICs have been traditionally handled. In particular, in this paper, the classic definition of the cross-section is revisited, putting into perspective the importance of the so-called “critical bits” in an FPGA design.

The GRSCRUB is an external Field Programmable Gate Array (FPGA) configuration supervisor developed by Cobham Gaisler as an Intellectual Property (IP) core. The GRSCRUB IP features different capabilities, such as programming and scrubbing, which prevents the accumulation of errors in the configuration memory of SRAM-based FPGAs. The GRSCRUB IP is currently compatible with the Xilinx Kintex UltraScale and Virtex-5 FPGA families. This white paper describes the GRSCRUB IP functionalities and evaluates the system by emulating faults in the target FPGA. Two evaluation designs are used: a static design and a design based on a LEON3FT processor core. The results demonstrate the GRSCRUB IP capability in correcting all faults injected in the FPGA configuration memory. In addition, in the case of the LEON3FT-based design, the GRSCRUB IP scrubbing operation allows uninterrupted software execution in the presence of correctable errors in the FPGA configuration memory by preventing the error build-up.

The Cobham Gaisler LEON4FT is a fault-tolerant synthesizable VHDL model of a 32-bit processor core, compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for System-on-Chip (SoC) designs. The processor is the basis of the Cobham Gaisler GR740, a radiation-tolerant SoC that features a quad-core LEON4FT processor, as well as several other peripherals. The Microsemi RTG4 Field Programmable Gate Array (FPGA) is fabricated using a low-power, 65 nm CMOS Flash technology, which is known to provide higher immunity to radiation-induced errors than SRAM-based FPGAs. This work performs a dynamic test of RTG4 FPGA embedding a LEON4FT-based SoC under heavy ion-induced single event effects. The results obtained demonstrate the effectiveness of the fault-tolerant techniques adopted at both device and design levels in a real application.

The LEON series of processors has enabled space missions during the two past decades. This paper discusses the past, present and future of the LEON series of SPARC 32-bit space-grade microprocessors and system-on-chip devices.

Thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based Field Programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. This paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. The controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. The HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.

Cobham Gaisler develops the LEON3FT SPARC V8 fault-tolerant microprocessor that is available both as IP cores part of an IP library (GRLIB) that allows users to design their own custom system-on-chip (SoC) designs, and also as part of ready-made designs and devices. Cobham Gaisler has recently added support for Microsemi IGLOO2, and experimental support for Microsemi radiation-tolerant RTG4, devices to GRLIB. The presentation will give an overview of LEON processor system-on-chip architectures that are currently supported for the latest generation Microsemi devices and will provide an overview of the steps and obstacles in porting existing IP cores to these devices.