The TRISTAN project aims to expand and industrialize the European RISC-V ecosystem to compete effectively with existing commercial alternatives. This initiative specifically targets the critical challenges in the development of Electronic Design Automation (EDA) tools, essential for RISC-V-based solutions, by leveraging the synergy between the open-source community and industrial solutions. This paper presents an overview of the current landscape of TRISTAN's EDA flow, highlighting specific tools and methodologies that streamline the early design phases of RISC-V-based systems. We explore the unique features of these tools, emphasizing how they complement each other to strengthen the overall design process.

This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned demonstrators, which will be used in their evaluation.

In common design flows of mixed-signal ASICs, the transition from system-level models to implementation-level models is executed in a manual process that carries potential for an efficiency gain by automation. This contribution addresses this aspect by showing and discussing an approach for efficient automated transitions from digital parts of Simulink models representing heterogeneous systems to VHDL and Verilog descriptions. It describes a design flow, in which a Simulink model representing a digital part of a mixed-signal ASIC is checked and optimized for automated generation of design rule compliant and more efficient digital hardware implementations. For this purpose, modeling guidelines and optimizations were implemented and integrated into an easily usable graphical user interface. Thereby, the strategy is based on considering and optimizing the digital part with respect to the surrounding heterogeneous system. An evaluation of the presented design flow is shown by applying the flow to an automotive hardware design.