Digital polar transmitter concepts based on RF-DA-converter recently proved the potential to significantly reduce power consumption. Furthermore, external component count as well as PCB area is minimized since no TX SAW filter is required and a single multimode, multiband power amplifier can be used.

This paper wants to clarify the important design parameters of the 45 nm process like matching, flicker noise, and offset from an analog designers' point of view. This paper describes a continuous time DeltaSigma ADC for voice coding applications.

A second order continuous time multibit (4bit) DeltaSigma-ADC for voice coding is implemented in a 65nm CMOS process. The dynamic range (DR) is 95dB over the voice bandwidth of 20-20 000Hz. Furthermore, by using a feed back architecture the need of an anti aliasing filter is eliminated. The input operational amplifier is chopped to eliminate flicker noise and offset. These improvements give way to a substantial simplification of the analog front end by allowing the absorption of the pre-amplifier and the antialiasing filter into the DeltaSigma-ADC. Thanks to the feedback structure the slew rate at the quantizer is limited and a power-efficient tracking ADC can be used. The total harmonic distortion (THD) is below -77dB at maximum input signal of 1.4Vpp. The ADC consumes 2.2mW from a 1.2V supply when clocked at 12MHz. The active area is 0.149 mm2

A 6 bit flash-ADC with 1.2 GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GSps, the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MSps we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.