This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.

This paper presents a design procedure for implementation of a matching network with spurious tones rejection using on-chip transformer for high speed DAC applications. Such circuits are complex to analyze and design, due to the higher order of the network. The presented design procedure involves matching the impedance at a desired center frequency based on the input impedance equation and with the aid of mathematical computational platform to avoid tedious mathematical derivations. A test case is considered with center frequency of 28GHz and detectable spurious tones at 30GHz and 26GHz to verify the proposed design procedure. The designed network matches a 50Ω load to a complex impedance of 12-j5.3 and simultaneously rejects the spurious tones by imposing notch filter at 30GHz and suppressing the other tone at 26GHz by 9.5dB.

Digital polar transmitter concepts based on RF-DA-converter recently proved the potential to significantly reduce power consumption. Furthermore, external component count as well as PCB area is minimized since no TX SAW filter is required and a single multimode, multiband power amplifier can be used.

A mixer and operational amplifier filter combination in 65 nm CMOS technology for DVB-H is presented. Special focus is laid on the design of the operational amplifier, which is a nested-Miller compensated, 3-stage feed-forward operational amplifier. Characteristic of the operational amplifier is the supply voltage of 2.5 V to enlarge the output signal swing of the operational amplifier. Cascodes are used avoiding the electrical destruction. The operational amplifier has a gain of 89 dB, a gain-bandwidth of 1.1 GHz, and phase margin of 53.3 deg at a load of 1 pF on each of the two differential outputs. The current consumption is 5.85 mA. This operational amplifier is used in a first-order low-pass filter after a passive mixer. This mixer-filter combination is characterized as well. A conversion gain of 24 dB and a bandwidth of 4 MHz are realized. Furthermore a noise figure of 16.1 dB and an IIP3 of +10dBm are achieved.