Switching frequency and switching losses are the dominating factors in power conversion applications. These factors can be controlled at technology development or at IC design with different trade-offs. In this paper we introduce a technique to measure safe operating area (SOA) under high frequency switching conditions - primarily, when the power LDMOS body diode is undergoing reverse-recovery. We show that this new SOA is more conservative than the electrical SOA and defines a diminished boundary for high frequency and high reverse injection operations. With this technique we look at the impact on specific design parameters in commonly used LDMOS topologies in an advanced BCD technology. Furthermore with the help of numerical simulations and careful metrological observations we discuss the phenomena leading to device performance limits useful for IC and device designers. Failure analysis of devices at product level and controlled failures created in standalone devices at wafer-level are examined.

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.

This paper discusses the challenges of making a MIM capacitor using a standard back end of line metal stack and a single additional mask. This required development of a capacitor dielectric would also serve as an antireflective coating for patterning 0.25 m metal interconnect lines or smaller. The paper also focuses on the characteristics of the analog capacitors. By improving this dual purpose oxide/SiON/oxide sandwich dielectric layer with special reflectivity properties, this novel integration forms a capacitor which possesses a combination of good voltage linearity or voltage coefficient, low dispersive behavior and hysteresis, and finally excellent matching with low leakage.

The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R/sub sp/) at the 20 V node. The 20 V rated lateral power device is difficult to optimize because modern VLSI processes tend to physically limit surface BV to about 13-19 V in planar devices. Here the structure performance is advanced by optimizing a Very-Thin-RESURF (VTR) region (VTR Xj=0.3 /spl mu/m). This work presents a planar VTR drain extended IGFET with best case BV=25 V and R/sub sp/=0.34 m/spl Omega//spl middot/cm/sup 2/@V/sub gs/=10 V using a compressed BiCMOS VLSI, 1 /spl mu/m technology. Structure variation and thermal performance are characterized.

This paper discusses the accomplishments of a Cooperative Research and Development Agreement between Texas Instruments and the National Renewable Energy Laboratory (NREL). Secondary ion mass spectrometry (SIMS) has showed the predicted reduction in impurity levels due to silicon upgrading during Spheral Solar processing. Transmission electron microscopy (TEM) has uncovered defects near the surface of the spheres that could play a significant role in controlling sphere efficiency. Radio-frequency photoconductance decay (RF-PCD) measurements have shown significant promise as a predictor of the electrical performance of silicon spheres. An RF-PCD system similar to NREL's has been constructed at Texas Instruments and is being prototyped as a real-time monitor of material quality during sphere processing