Switching frequency and switching losses are the dominating factors in power conversion applications. These factors can be controlled at technology development or at IC design with different trade-offs. In this paper we introduce a technique to measure safe operating area (SOA) under high frequency switching conditions - primarily, when the power LDMOS body diode is undergoing reverse-recovery. We show that this new SOA is more conservative than the electrical SOA and defines a diminished boundary for high frequency and high reverse injection operations. With this technique we look at the impact on specific design parameters in commonly used LDMOS topologies in an advanced BCD technology. Furthermore with the help of numerical simulations and careful metrological observations we discuss the phenomena leading to device performance limits useful for IC and device designers. Failure analysis of devices at product level and controlled failures created in standalone devices at wafer-level are examined.

A novel, high voltage, dual-gate lateral double diffusion MOSFET (LDMOS) with both p-type and n-type conduction is experimentally demonstrated using reduced surface field (RESURF) Si bulk technology. The p-n bimodal LDMOS can enhance drain saturation current by at least 30% with limited cost penalty compared to traditional n-LDMOS. Detailed analysis on the bimodal conduction LDMOS operation and DC output and temperature characteristics is presented. A simplified driving scheme is proposed to drive the dual-gate, p-n bimodal conduction LDMOS.

Failure during reverse recovery of an IC power diode is examined. It is shown how one-dimensional diode behavior together with mixed-mode tcad can be used to predict safe operating conditions for the actual two-dimensional case.

A peculiar temperature mismatch between a power LDMOS and its sense FET develops over time resulting in yield losses. The anomaly is traced to trapped charge in the power LDMOS that arises from a seemingly unrelated change in the hydrogen anneal temperature in the back end. The physical mechanism leading to the anomaly and the interaction between temperature mismatch and metal layout are presented.

Although silicon roadmaps have had a major impact on the progress of semiconductor technology, roadmap emphasis has largely been in the digital arena. Integration of high-voltage and high-current devices into chip designs has tended to follow the original roadmap with a delay of a year or more owing to both economic and technological factors. The resulting 'mixed-signal' roadmaps tend to be less structured company-to-company.. since more opportunities exist for a variety of approaches. To aid in the understanding of mixed-signal roadmaps, this paper summarises some of the requirements for including power devices into an existing BiCMOS technology. Some of the principles that determine the integration process are described.

This paper presents a new method of enhancing the SOA of n-channel Ldmos transistors. Attention is focused on those applications where “Electrical SOA” is important and where the power pulse time is typically a few µs or less. Typical applications include gate drives, H-bridge commutation, and self-protection against ESD pulses.

An integrated lateral output device is presented which has a very high degree of ESD robustness. The high ESD robustness is achieved with negligible increase in the overall size of the output device. Such an integrated device is ideally suited for high voltage output pins requiring low on-state resistance (Rdson) with stringent system level IEC requirements.

A new pseudo-vertical integrated npn bipolar transistor with variable sustaining and trigger voltages is presented in this paper. It is shown that the sustaining voltage can be tuned to obtain the required high value. These devices are realized in a junction isolated (JI) mixed-signal power BiCMOS technology with maximum breakdown voltage requirements in excess of 60V. The ESD robustness of these bipolar transistors is verified using transmission line pulse (TLP) and HBM (human body model) measurements. It is now possible to use a single bipolar transistor as an ESD protection device for a high voltage pin application instead of using stacked bipolar devices. The net result is a better control and possible reduction in overall die area.

A novel 2D-simulation method is used to simulate major aspects of the formation of the current filament and to help understand and predict the level of ESD robustness in lateral power devices

Safe operating area limits for large Ldmos are shown to be due to a thermal instability mechanism initiated by avalanche generated carriers which turn-on the parasitic bipolar transistor. An analytic model is described and is shown to agree well with experimental data.

A simple method for demonstrating filamentation in lateral power devices is described. The results show that "mathematically perfect" junctions need to have defects added to initiate filamentation. When this is done, two-dimensional simulations exhibit behavior that is seen in practice. One application of these results is the design of protection structures

Measured SOA is compared with simulations for field gap LDMOS transistors. The utility of an n-type "resurf" or "nfield" implant under the field oxide is considered. For a fixed VDS, it is shown that there is an optimum value of nfield dose.

The trade-off between breakdown voltage and on-resistance is a well-known feature of both lateral and vertical DMOS transistors. The trade-offs and restrictions imposed by the “safe operating area” are less familiar. The SOA defines limits on the excursion of the operating point in the Id-Vds plane. To be correct, the SOA should also include thermal limitations; however, these can be treated separately. In this paper, we focus on the “electrical SOA”, which is defined by a specific boundary line in the Id-Vds plane. Although the LDMOS SOA has been discussed in a number of papers, the details of the device physics that determine the SOA boundary are still somewhat unclear and further work is needed. The main purpose of this paper is to investigate device behaviour in the neighborhood of the SOA boundary and then use these results to predict the SOA. We consider devices with and without drain extensions using a self-aligned body diffusion. The predicted SOA is shown to be in good agreement with measurements for both types of LDMOS. Current flow within the device is examined in detail. The observed SOA is shown to be consistent with the silicon power density limit, a fundamental characteristic of silicon devices. Finally, we show how a simplified two-terminal model of the drain region can be used to demonstrate the behaviour of the LDMOS as it approaches snap-back. This approach is analogous to that previously used to model the onset of avalanche initiated second breakdown in bipolar transistors (hower and Reddi, 1970)