An active coplanar circulator for Q-band operation based on lattice matched InAlAs/InGaAs/InP HFETs has been designed and fabricated. The active devices have a gate-width of WG=6×20 μm and T-gates with a gate-length of LG =0.25 μm. The circuit is fully passivated, contains all matching and biasing networks on chip and operates under zero volt gate bias. Over the entire frequency range the input reflection of the circulator is better than -15 dB and the isolation between the transmit and the receive path is better than -30 dB which is attributed to the extremely low feedback capacitance of the InP-based HFETs

The influence of proximity correction on device yield and process latitude in electron-beam fabrication of short-period metal-semiconductor-metal (MSM) photodetectors is investigated. A modified Fourier-transform deconvolution method is used for proximity correction. Scattering data is obtained from Monte Carlo simulation, without the need for costly experimental parameter determination. Proximity correction leads to a significant improvement in device yield and process latitude. Figures of merit for latitude enhancement typically are in the range 2…10, depending on device geometry and process context. For a field-effect transistor compatible process technology, MSM devices with finger periods down to 200 nm can be realized using proximity corrected exposure.

A family of one, two and three stage monolithic amplifiers on InP substrate for W-band applications are presented. The circuits are realized with lattice matched InAlAs-InGaAs-InP HEMTs with a gate-width of WG=2×40 μm and T-gates with a gate-length of L G=0.25 μm. Coplanar waveguides and lumped elements are used for the matching and biasing networks. The circuits are fully passivated and contain common ports for the gate and the drain bias. A gain of 5.5, 11 and 14.5 dB and an input and output matching better than -10 dB were achieved for the one, two and three stage amplifiers at 80 GHz, respectively. The measured results show a good scaling of the achieved gain between the one and the multiple stage amplifiers and a good correlation with the simulated results

The search for suitable ways to improve the high electron mobility transistors (HEMT's) device performances has stimulated the turbulent research work on pseudomorphic layer structures. Recent interest has been focused on pseudomorphic InAlAs/InGaAs HEMTs. In this paper we report on the design and fabrication of In0.52Al0.48As/InxGa1-xAs (0.53 < x < 1.0)-pseudomorphic HEMTs. The main subject of the simulation and experimental work is the design of the channel to allow a maximum InAs molefraction ion while maintaining excellent device performance. The general results of our investigation are that the current handling capability and the high speed performance improves with x, while the breakdown voltage Continuously degrades with increasing x. From our investigation an indium molefraction of x = 0.7 was found to be optimum for the high speed performance.

A systematic experimental study on the mechanisms which are inducing device breakdown in the off-state in L G=0.28 µ m gate-length pseudomorphic InAlAs/In x Ga1- x As (0.53< x<0.7) High Electron Mobility Transistors on InP substrate is presented. The study identifies the present limitations of this type of device made with this material system. The investigation encompasses temperature- and mole fractional dependent two-terminal and three-terminal dc-measurements. The results of the investigation clarify that breakdown is a combined process of thermionic field emission and impact ionization. Up to high drain bias, thermionic field emission is the dominant process, only at very high drain bias impact ionization occurs. The experimental results also indicate that off-state breakdown is surface related. The drain-source breakdown voltages were determined to be V BRDS=8 V, 5.9 V, 5.2 V, 4.3 V, 2.5 V for x=0.53, 0.59, 0.62, 0.65 and x=0.7, respectively. The two-terminal gate-drain breakdown voltages at room-temperature were determined to be V BRGD=11.9 V, 11.3 V, 7.9 V, 7.2 V, 6.7 V for x=0.53, 0.59, 0.62, 0.65 and x=0.7, respectively.

A systematic investigation on the breakdown mechanisms in the on-state mode of operation of pseudomorphic InAlAs/In/sub x/Ga/sub 1-x/As (0.53>

A new type of a quasi one-dimensional planar field-effect-transistor (FET) with two lateral and symmetric in-plane-gate electrodes (IPG) is realized. The vertical layer sequence consists of a GaAs/AlGaAs heterostructure and a δ-doped pseudomorphic InGaAs quantum well with a high-density two-dimensional electron gas (2DEG). The device configuration results in a strong lateral concentration of the confining electric field in the 2DEG plane. The fabricated devices operate excellently at room temperature with maximum currents (IDS) above 0.3 mA and transconductance (gm) values of 0.2 mS. Perfect pinch-off is achieved by a negative gate-voltage. Devices with planar arrays of quasi one-dimensional channels exhibit IDS > 6 mA and gm = 5 mS. A PMMA electron beam lithography process followed by a selective isolation implantation is used for the fabrication of IPG-FET devices.

A systematic investigation on the breakdown mechanisms in the on-state mode of operation of pseudomorphic InAlAs/InxGa1-xAs (0.53<x<0.7) HEMTs is presented. From temperature- and composition dependent measurements and burn-out experiments it is demonstrated that on-state breakdown in these devices is dominated by impact ionization and that the location of on state breakdown is the channel layer. The on-state breakdown voltage drops with increasing indium mole fraction in the channel layer

Theoretical and experimental investigations of methods to obtain T- and Γ-shaped sub-100 nm gates using electron-beam lithography, multilayer resist schemes and lift-off are reported. A resist profile simulation tool, based on Monte Carlo electron scattering calculation and an adaptive string algorithm, is combined with an experimentally determined solubility database for various resist/developer pairs. This provides a very accurate description of the profile formation process for arbitrary resist/substrate stacks and excellent agreement between simulated and experimental resist profiles is achieved. Limitations due to forward scattering and the influence of development conditions are discussed. Using optimized exposure and development parameters, sub-100 nm T and Γ gates with very low end-to-end resistances can be fabricated without sacrificing process latitudes.

Time-resolved investigations on the photoluminescence of GaAs/AlxGa1-xAs quantum wires as a function of the wire width and the potential well depth indicate a reduction of the energy relaxation in quasi-one-dimensional (1D) systems. The systematic change of the wire width and potential well depth of the quantum wires with mask widths down to 40 nm were realized by ion-implantation-induced intermixing of quantum wells. Lifetime measurements on the high-energy side of the quantum wire emission yield increased decay times for the smallest wires. This is consistent with our observation of increased carrier temperatures and slowed cooling in the quantum wires with increasing carrier confinement. We explain the reduction of the relaxation with the decreased possibility for the scattering particles to fulfill both energy and momentum relaxation in wires with gradually increasing 1D behavior.

A three stage 28 GHz InP MMIC coplanar waveguide implifier with 27 dB gain over the frequency band from 26 to 32 GHz has been developed. The circuit is fully passivated with Si3N4 and includes all necessary elements for input/output matching and bias decoupling. As active devices 0-25 mum lattice matched InAlAs/InGaAs HEMTs were used. The chip dimensions are 2.4 x 2.0 mm2.

The process technology of fully passivated T-shaped 0.18-mu-m gate length InAlAs/InGaAs/InP HFETs is described. Using material selective etchants, devices realised with this process yielded gate breakdown voltages in excess of 8 V and drain source breakdown voltages in excess of 5 V. The excellent gate characteristics lead to a noise figure of 0.75 dB at 18 GHz with 13 dB associated gain. The extrapolated maximum frequency of oscillation was determined to be f(max) = 290 GHz.

The process technology of fully passivated T-shaped 0.18 μm gate length InAlAs/GaAs/InP HFETs is described. Using material selective etchants, devices realised with this process yielded gate breakdown voltages in excess of 8 V and drain source breakdown voltages in excess of 8 V and drain source breakdown voltages in excess of 5 V. The excellent gate characteristics lead to a noise figure of 0.75 dB at 18 GHz with 13dB associated gain. The extrapolated maximum frequency of osciallation was determined to be fmax = 290 GHz

The process technology of fully passivated T-shaped 0.18 mu m gate length InAlAs/InGaAs/InP HFETs is described. Using material selective etchants, devices realised with this process yielded gate breakdown voltages in excess of 8 V and drain source breakdown voltages in excess of 5 V. The excellent gate characteristics lead to a noise figure of 0.75 dB at 18 GHz with 13 dB associated gain. The extr...

We have fabricated III–V semiconductor quantum wires which display a variety of novel transport and optical phenomena. For the definition of structures with widths down to 40 nm high resolution electron beam lithography and dry etching have been used. For the observation of dimensionality dependent effects in optical spectra buried quantum wires have been developed by overgrowth of dry etched structures and implantation induced intermixing. The physical properties of the nanometer structures have been analyzed by magnetotransport studies and emission spectroscopy.

We have investigated the sidewall recombination in dry-etched GaAs/GaAlAs wires with widths between 12 μm and 300 nm using picosecond spectroscopy. The wires were fabricated with electron beam lithography and different reactive ion etching processes. The excitonic lifetimes decrease strongly with decreasing wire widths due to sidewall recombination. Using a model calculation to fit the experimentally observed width dependence of the lifetimes the surface recombination velocity is determined to be S=2×106 cm/s at 50 K. S increases with temperature and is independent of the etching process.