In this paper, we review the performance, reliability, and robustness of the current 4H-SiC power DMOSFETs. Due to advances in device and materials technology, high power, large area 4H-SiC power DMOSFETs (1200 V, 67 A and 3000 V, 30 A) can be fabricated with reasonable yields. The availability of large area devices has enabled the demonstration of the first MW class, all SiC power modules. Evaluations of 1200 V 4H-SiC DMOSFETs showed that the devices offer avalanche power exceeding those of commercially available silicon power MOSFETs, and have the sufficient short circuit robustness required in most motor drive applications. A recent TDDB study showed that the gate oxides in 4H-SiC MOSFETs have good reliability, with a 100-year lifetime at 375oC if Eox is limited to 3.9 MV/cm. Future work on MOS reliability should be focused on Vth shifts, instead of catastrophic failures of gate oxides.

A hetero-epitaxial 3C-SiC growth process in a low-pressure hot-wall CVD reactor has been developed on planar Si (100) substrates. The growth rate achieved for this process was about 10 μm/h. The process consists of silane/propane/hydrogen chemistry with HCl used as a growth additive to increase the growth rate. 3C-SiC has also been grown on 22, 52 and 123 +m deep etched MEMS structures formed by DRIE of (100) Si at a rate of about 8 +m/h. Secondary electron microscopy (SEM), atomic force microscopy (AFM) and X-ray diffraction (XRD) were used to analyze the quality of the 3C-SiC films.

1000 V Bipolar Junction Transistor and integrated Darlington pairs with high current gain have been developed in 4H-SiC. The 3.38 mm x 3.38 mm BJT devices with an active area of 3 mm x 3 mm showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm2, at a forward voltage drop of 2 V. A common-emitter current gain of 40 was measured on these devices. A specific on-resistance of 6.0 mW-cm2 was observed at room temperature. The onresistance increases at higher temperatures, while the current gain decreases to 30 at 275°C. In addition, an integrated Darlington pair with an active area of 3 mm x 3 mm showed a collector current of 30 A at a forward drop of 4 V at room temperature. A current gain of 2400 was measured on these devices. A BVCEO of 1000 V was measured on both of these devices.

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.

SiC power BJTs have been developed over the last five years into a sufficiently mature technology (1-5). The reliability and applications of these devices are now being studied. This paper summarizes the evolution of this development culminating into the most recent performance of the 1600 V, 20 A devices with a current gain of 40 in the linear region, a forced current gain of 27 in the saturation region and a specific on-resistance of 4.5 mohm-cm(2).

A silicon carbide power module has been developed to demonstrate a high-temperature, 10 kW AC drive application. Several goals for this development include temperature dependent parameter evaluation of parallel-connected transistors and junction barrier Schottky diodes at 150 /spl deg/C operating temperature. Next, design of a high-thermal conductivity substrate to cool the modules based on predicted losses. Finally the integration into a variable speed AC drive using a DSP-based V/F motor controller. Test results for the 10 kW AC drive are provided to demonstrate power module performance up to 180 /spl deg/C.

Bipolar Junction Transistors (BJT) and integrated Darlington pairs have been developed in 4H-SiC. The 3 mm x 3 mm BJTs show an on-state current of 20 A at a forward drop of 1.2 V at room temperature. The smaller 2 mm x 2 mm devices were tested up to 325 degreesC. The on-resistance increases and the current gain reduces with increasing temperature. The reverse leakage current was measured to be less than 40 muA at 1000 V and 325 degreesC. Inductive switching at 1000 V, 5 A shows extremely fast turn-on and turn-off behavior.

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm(2)) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/mus in these devices.

The high-temperature operation of a silicon carbide gate turn-off thyristor is evaluated for use in inductively loaded switching circuits. Compared to purely resistive load elements, inductive loads subject the switching de-ice to higher internal power dissipation. The ability of silicon carbide components to operate at elevated temperatures and high power dissipations are important factors for their use in future power conversion/control systems. In this work, a maximum current density of 540 A/cm(2) at 600 V was switched at a frequency of 2 kHz and at several case temperatures up to 150degreesC. The turn-off and turn-on characteristics of the thyristor are discussed.

Localized doping in SiC is done by ion implantation because dopants do not diffuse at acceptable rates until the annealing temperature exceeds 1800°C. During this process, SiC surface has to be protected up to high temperatures. The authors found We have found a solution to this problem by capping the AlN cap with a BN cap and then, after the sample has been annealed, ion milling off the BN and etching off the AIN as before. In this paper they show that this cap can protect the SiC surface up to temperatures at least as high as 1700°C. This is done by observing the surface in a scanning electron microscope (SEM) after the wafer has been annealed and the caps have been removed. They also describe the properties of the BN layer that was deposited by pulsed laser deposition (PLD) by looking its surface in the SEM; examining its structure with Fourier transform infrared (FTIR) spectroscopy, X-ray diffraction (XRD), and cross section transmission electron microscopy (XTEM), and determining if there was any chemical -intermixing of the layers using Auger electron spectroscopy (AES) depth profiling

Localized doping in SiC is done by ion implantation because dopants do not diffuse at acceptable rates until the annealing temperature exceeds 1800/spl deg/C. During this process, SiC surface has to be protected up to high temperatures. The authors found We have found a solution to this problem by capping the AlN cap with a BN cap and then, after the sample has been annealed, ion milling off the BN and etching off the AIN as before. In this paper they show that this cap can protect the SiC surface up to temperatures at least as high as 1700/spl deg/C. This is done by observing the surface in a scanning electron microscope (SEM) after the wafer has been annealed and the caps have been removed. They also describe the properties of the BN layer that was deposited by pulsed laser deposition (PLD) by looking its surface in the SEM; examining its structure with Fourier transform infrared (FTIR) spectroscopy, X-ray diffraction (XRD), and cross section transmission electron microscopy (XTEM), and determining if there was any chemical -intermixing of the layers using Auger electron spectroscopy (AES) depth profiling.

Ni/WSi/Ti/Pt Ohmic contacts to n-SiC were investigated as a function of annealing temperatures up to 1000 °C. Annealing at temperatures between 950 and 1000 °C yielded excellent Ohmic behavior. At these temperatures the contact–SiC interface was smooth, defect free, and characterized by a narrow Ni2Si reaction region. The annealed contacts possessed atomically smooth surface morphologies and exhibited minimal contact expansion. The residual carbon, resultant from SiC decompositon and reaction with Ni to form Ni2Si, was constrained by reaction with the WSi and Ti layers forming carbide phases of W and Ti spatially distant from the metal semiconductor interface. Our results demonstrate that the Ni/WSi/Ti/Pt composite Ohmic contact maintains the desirable electrical properties associated with Ni contacts and possesses excellent interfacial, compositional, and surface properties which are required for reliable high power and high temperature device operation.

Pendeo Epitaxy is a type of Lateral Epitaxial Overgrowth (LEO) that instead of using a dielectric buffer layer, uses an etched substrate to grow laterally without an interface layer. We report the first successful growth of 3C-SiC on Si using Pendeo epitaxy. Rectangular stripes of 3C-SiC on (100) Si substrates were fabricated, along both the [110] and [100] directions. Pendeo epi was only observed for columns parallel to [001], indicating a preferred growth facet for Pendeo epi of 3C-SiC on Si. SEM and TEM investigations were performed to assess the material quality of the Pendeo 3C-SiC material. Films were grown for 60 min at 1310°C and film coalescence was achieved without evidence of voids where the growth fronts joined. TEM data indicate not only the growth of vertical and lateral 3C-SiC on the 3C-SiC seed layer but direct nucleation of 3C-SiC on the exposed Si columns side wall and trench bottom, despite the lack of a carbonization procedure. The quality of the Pendeo 3C-SiC film appears to be of high quality indicating that Pendeo epi of 3C-SiC on low-cost, large-diameter Si substrates may prove to be a cost effective way to grow device-grade SiC layers on Si substrates for device applications.

Shallow implantations of Ga ions were performed on p-type 6H-SiC by conventional broad area implantation, and the physical and electrical properties of the Ga-SiC system upon high temperature annealing were examined, in order to understand the role of Ga in ohmic contact formation. The shallow implantation depth (30 nm) and high Ga doses ranging between 1×10 15 and 1×10 16 cm −2 , resulted in heavy surface damage as observed by atomic force microscopy surveys. Samples annealed using a sacrificial SiC wafer as a capping layer, showed no improvement in surface roughness for annealing up to 1300 °C, while at 1500 °C, surface roughness was markedly changed. At 1600 °C the surface re-crystallized back to the stepped terraced morphology of the un-implanted surface but with significantly larger step and terrace size. At this annealing temperature, heavy Ga loss from the surface was observed. Samples annealed at 1500 °C using an AlN capping layer, showed significant outdiffusion of Si into the AlN layer, and redistribution of Ga within the SiC surface. The contact resistance of as-implanted and annealed samples using the sacrificial SiC wafer, were measured by the TLM method. Although contact resistance was found to decrease with increasing annealing temperature, sheet resistance increased, and contact resistance values were higher than expected, indicating that the heavy loss of Ga atoms contributed to the increased levels of contact resistance.

Lateral Epitaxial Overgrowth (LEO) experiments on 3C-SiC were conducted on patterned substrates. Due to the high CVD growth temperatures required for high-quality single-crystal 3C-SiC, dielectric mask materials with higher thermal stability than SiO2 were used. Experiments were performed with amorphous Si3N4 deposited via PECVD and AIN, deposited both by PLD and MOCVD. These masks were deposited and patterned on (100) Si substrates containing a 4 mum 3C-SiC epitaxial layer grown using a standard 3C-SiC growth process. Single crystal 3C-SiC was regrown in the mask window regions. However, polycrystalline 3C-SiC nucleated on the mask stripes for the growth conditions studied. Pendeo epitaxy (PE) was performed on the same material where the 3C-SiC epilayer was etched to form 3C-SiC stripes on a (100) Si substrate. It appears that Pendeo epitaxy was achieved with lateral and vertical growth on the 3C-SiC columns having been observed.

A SiC high temperature amplifier circuit has been developed using discrete SiC depletion mode transistors. The amplifier open loop gain decreases by only 4 dB over the temperature range of 298 to 573 K at 1 kHz. From radiation effects results on the discrete devices included in this paper it is expected that this amplifier could survive a severe radiation environment to a total dose of 100 Mrad and neutron fluence exceeding 1015 n/cm2. The radiation results also suggest that the amplifier will be less susceptible to radiation at high temperatures.