Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm 2 ) such that essentially no failures (0.01 FIT/cm 2 ) are expected at 400V drain-source bias (V DS ) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given V DS operation condition, the FIT/cm 2 can be decreased by 10 - 100 times, depending on the V DS value. This allows operation at about 75V higher V DS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

For high power full SiC modules, the application requires highly reliable and robust 4H-SiC diodes in parallel with SiC MOSFETs. This work introduces new large size (50A rated) 1200V and 1700V 4H-SiC diodes which exhibit excellent performance under high temperature reverse bias (HTRB) and high voltage high temperature humidity (HV -H3TRB) conditions without sacrificing critical device performance such as forward voltage dropr $\mathbf{(Vf)}$ , Schottky Barrier height and ideality factor, and reverse leakage current. In this work, we have improved the device integration scheme for diode manufacturing, which enabled the successful completion of HTRB and HV-H3TRB qualification for automotive application.

Silicon carbide (SiC) metal-oxide semiconductor (MOS) power devices such as metal-oxide semiconductor field-effect transistors (MOSFETs) require a stable and low defect-density interface, and a high-quality dielectric, for good device performance and reliability. Notably, the interface and dielectric properties determine the threshold voltage stability, the field-effect channel mobility, and the device lifetime as limited by dielectric breakdown in both the forward on-state and reverse blocking conditions. Here we discuss the present state of SiC MOS processing and properties and point to directions for future development. Important items to address are: 1) interface passivation approaches; 2) dielectrics; 3) device design; and 4) in-depth measurements of the interface quality and reliability.

The demand is rapidly increasing for SiC MOSFETs and diodes for power electronic conversion semiconductor (PECS) applications such as electrified vehicle charging and traction, energy storage systems and industrial power supplies. These applications employ a high quantity of large-area die per system while demanding high system-level reliability under aggressive electrical and environmental operating conditions. In addition, SiC devices exhibit some failure mechanisms that are less severe than, or non-existent, in Si devices. This situation demands thorough and novel device reliability characterization and quantification. It is also driving the development of industry consortia standards and guidelines at a much faster rate, and relatively earlier in the technology maturation phase, than occurred in the Si industry. In this paper, I will review some of the key published reliability performance data, stress procedure methodologies used, and implications for key applications. I will also compare and contrast the existing guideline and standard documents and suggest directions that are being explored for future documents. I will also discuss how future guidelines and standards are being developed to cover the SiC-specific failure mechanisms for representative mission profiles for some key applications, particularly electrified vehicles.

With the steep expansion of the n-type 4H-SiC power metal-oxide-semiconductor field-effect transistor (MOSFET) market space, gate oxide reliability is gaining more and more attention. Although there exist several reports dealing with the bias temperature instability (BTI) under both positive and negative gate biases, gate oxide lifetime evaluations predominantly focus on positive gate bias time-dependent dielectric breakdown (TDDB) stresses for n-channel SiC MOSFETs. In this work we address that gap. From the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress. Also, in this work the correlation between failure location in a MOSFET unit cell and the failure signatures during TDDB stress have been established, and an explanation from a device physics standpoint has been provided. The identification of the failure location in the unit cell from in-situ gate leakage data without the need of physical failure analysis can turn out to be key during the early phase of a new process development activity.

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

Power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state and above a VDS threshold for that device. Typically, the SEB failure rate is measured at a high blocking voltage, with the source and gate at ground potential. Here the effect of a negative gate bias, commonly applied during MOSFET switching to the blocking state, on the SEB failure rate is examined. It is observed that the SEB failure rate is only weakly dependent on the negative gate bias, because it does not significantly affect the peak field in the drift region where avalanche breakdown is initiated. A negative gate bias of -8VGS in the device blocking state at 1100VDS only results in a 6% increase in the MOSFET SEB failure rate.

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of 4H-SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large population of medium voltage SiC MOSFETs. Constant current stress at a current equal to the device forward rating was applied for 1000 hours. No degradation of any device parameter was observed for 3 lots of devices at both the 3.3 kV and 10 kV voltage rating.

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

High performance 15 kV n-GTOs were demonstrated for the first time in 4H-SiC. The device utilized a 140 μm thick, lightly doped n-type drift layer, with 1450°C lifetime enhancement oxidation, which resulted in a carrier lifetime of 17.5 μs. The p+ backside injector layer was thinned to minimize parasitic resistances. A room temperature forward voltage drop of 5.18 V was observed at a current density of 100A/cm2. A 1 cm2 device showed a leakage current of 0.17 μA at 15 kV. The 4H-SiC n-GTO showed latching characteristics, and showed a turn-off time of 170 ns in a resistive load switching setup, which represents about a factor of 45 improvement in turn-off speed over 4H-SiC p-GTOs with comparable voltage and current ratings.

The current voltage characteristics and the low-frequency noise in high voltage 4H-SiC junction barrier Schottky diodes irradiated with high energy (15 MeV) protons were studied at different temperatures and irradiation doses Φ from 3 × 1012 cm−2 to 1 × 1014 cm−2. Irradiation led to the increase of the base resistance and the appearance of slow relaxation processes at small, V ≤ 0.2 V, and at rather high, V ≥ 2 V, forward voltages. The characteristic times of these relaxation processes ranged from ∼1 μs to 103 s. The exponential part of the current-voltage characteristic was only weakly affected by irradiation. The temperature dependence of the base resistance changed exponentially with temperature with activation energy Ea ∼ 0.6 eV, indicating that the Z1/2 level plays a dominant role in this process. The temperature increase also led to the increase of the ideality factor from 1.05 at 25 °C to 1.1 at 172 °C. At elevated temperatures and high forward voltages V > 2–4 V, the current voltage characteristics tend to be super-linear. It is concluded that at high voltages, the space charge limited current of majority carriers (electrons) and hole injection from the p-n regions play an important role in the formation of the current voltage characteristic. The frequency dependences of noise spectral density S of proton irradiated Schottky diodes have the unusual form of S ∼ 1/f 0.5.

For the first time, a new SiC chip and module combination is designed and characterized to offer optimal performance and cost. The chip is a 1200 V, 13 mOmega SiC MOSFET designed for a 1/2 bridge power module with a possible reduced number of individual gate resistors inside the module and improved immunity to shoot-through. The MOSFET die has a minimal increase in RDSON from 13 mOmega at 25 deg C to only 20-22 mOmega at 175 deg C, and low CRSS of 12pF. Under normal operating conditions and thermal environment defined in the manuscript, each SiC MOSFET die is capable of 100-140 A of current under normal operating conditions of TC from 25 deg C to 95deg C, TJmax of 175 deg C. In a 1/2 bridge configuration, using a TO247 with no Kelvin contact, total switching energy loss is a relatively temperature independent 2.6 mJ at 600 V, 80A, even though designed for < 30kHz. The compact 41mm module allows up to four MOSFETs per switch position, IDS rating of 340 A (approximately seven times higher than Si baseline modules) and lower RDSON (3.25 mOmega) than commercial SiC modules over twice its size.

In this paper, we present our latest results on 650 V 4H-SiC DMOSFET developments for dual-side sintered power modules in electric drive vehicles. A low specific on-resistance (R sp , on ) of 1.8 mΩ⋅cm 2 has been achieved on 650 V, 7 mΩ 4H-SiC DMOSFETs at 25°C, which increases to 2.4 mΩ⋅cm 2 at 150°C. For the first time, the DMOSFET chip is designed specifically for use in dual-side soldering and sintering processes, and a 650 V, 1.7 mΩ SiC DMOSFET multichip half bridge power module has been built using the wirebond-free assembly. Compared to a similarly rated Si IGBT module, the conduction and switching losses were reduced by 80% and ~50%, respectively.

Electron irradiation of high voltage Ni/4H-SiC Schottky diodes with the dose Φ=(0.2-7)×1016cm-2 led to increase in the base resistance, appearance of slow relaxation processes at extremely small currents, and increase of the low frequency noise. On exponential part of the current-voltage characteristics and on linear part of current-voltage characteristics in non-irradiated samples, low frequency noise always has the form of the 1/f noise. On linear part of the current-voltage characteristics in irradiated diodes the generation recombination (GR) noise predominates. Temperature dependences of the base resistivity and character of GR noise indicate that mainly Z1/2 center contributes to the change in the parameters of irradiated samples. Capture cross section of this level, obtained from noise measurements, is within the range (8×10-16-2×10-15) cm2 and only weakly depends on temperature.

High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

This paper discusses the reliability performance of Wolfspeed GaN/AIGaN high electron mobility transistor (HEMT) MMIC released process technologies, fabricated on 100 mm high purity semi-insulating (HPSI) 4H-SiC substrates. The intrinsic reliability performances of the 28 V and 40 V technologies, with 400 nm and 250 nm gate length, have been characterized with DC accelerated life test (DC-ALT), for which ohmic contact inter diffusion is the wear-out mechanism, and is accelerated by temperature and current. The intrinsic reliability performance of the 50 V technologies, with 400 nm gate length, have been characterized with RF-ALT, for which source-connected second field plate void coalescence is the wear-out mechanism which is accelerated by temperature. In spite of the differences in the accelerated test methodologies and wear-out mechanisms, all of the Wolfspeed GaN-on-SiC technologies demonstrate high and similar predicted lifetimes at their respective maximum recommended operating conditions. The reliability performance is supported with successful technology qualifications with zero failures, and volume manufacturing with a demonstrated low field failure rate.

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation, with high MOS gate oxide field in the on-state, and high drift and termination fields in the blocking state. Moreover, silicon carbide devices typically experience higher fields than comparable Si devices due to channel and drift property differences. SiC MOSFET threshold voltage stability and gate oxide lifetime under high gate oxide field are observed to follow the same functional form as Si devices. SiC MOSFETs demonstrate intrinsic oxide lifetime greater than 10(7) hrs in time-dependent dielectric breakdown (TDDB) testing. Accelerated high-temperature reverse-bias (HTRB) testing above the rated voltage reveals similarly long lifetime under high drift fields. The device failure rate due to terrestrial neutron single-event burnout (SEB) is shown to be comparable or superior to that of Si devices. Results demonstrate the reliability of SiC MOSFETs under high-field operation.

This work explores the effects of extended epitaxial defects on 4H-SiC power devices. Advanced defect mapping techniques were used on large quantities of power device wafers, and data was aggregated to correlate device electrical characteristics to defect content. 1200 V class Junction Barrier Schottky (JBS) diodes and MOSFETs were examined in this manner; higher voltage 3.3 kV class devices were examined as well. 3C inclusions and triangular defects, as well as heavily decorated substrate scratches, were found to be device killing defects. Other defects were found to have negligible impacts on device yield, even in the case of extremely high threading dislocation content. Defect impacts on device reliability was explored on MOS-gate structures, as well as long-term device blocking tests on both MOSFETs and JBS diodes. Devices that passed on-wafer electrical parametric tests were found to operate reliably in these tests, regardless of defect content.