Interleaving architecture extends high performance, low cost, transition mode PFC to higher power levels. Because the existing Master Slave interleaving control requires a slave channel operating in DCM mode, switching loss and EMI noise are increased. In this paper, a novel interleaving control method is proposed without using the Master Slave concept. The proposed method is able to realize 180 degrees phase-shift as well as true transition mode operation to achieve the optimal system performance.

This paper presents a practical approach to accurately measure the in-circuit power loss of an integrated power electronics module. Based on several reasonable assumptions, the heat flux out of the module is related to the temperature drop across the thermal resistance material in the heat dissipation path. By performing a calibration experiment, the total dissipated heat can be identified. The experimental results prove the high accuracy of this measurement method. This measurement method can be extended to other situations when the assumptions that are applicable to this experiment are satisfied.

In this paper, the concept of high frequency operation to shrink the EMI filter and inductor size in the PFC circuit is demonstrated. A 600 kHz single switch CCM boost PFC with 92% full load efficiency at 90 VAC input is developed with the Infineon newly developed CoolMOS and SiC diode devices. Both the EMI filter and the inductor size are greatly reduced. Further more, a new two-stage PFC architecture is introduced. This enables the PFC to run at 1 MHz with 92.8% full load efficiency. At such high operating frequency, the EMI filter and inductor size is further reduced. For the second stage in this structure, a high efficiency, and high power density voltage doubler is proposed. The measured full load efficiency of the voltage doubler prototype is 99%. Interleaving multi-phase high frequency PFC architecture is also introduced. The ability to reduce the EMI filter size by increase the EMI noise frequency is discussed and demonstrated.

For high power application the interleaved multichannel PFC is becoming more and more popular. It can effectively reduce the input ripple current due to the ripple cancellation effect. It is generally believed that the reduced input ripple current will lower down the DM EMI noise magnitude, which will make the DM Alter smaller. However, for most of today's PFC, running in the frequency range of 75 kHz ~ 150 kHz, the conventional 2-channel interleaving technique cannot help to reduce the EMI filter size at all. In this switching frequency range, the EMI filter design is based on the 2 nd order harmonic, which cannot be reduced by the conventional interleaving. In this paper, a 2-channel PFC operating with 90 degree phase shift is introduced. It can cancel the 2 nd order harmonic and reduce the 3 rd order harmonic, and the EMI filter size can be reduced. This novel interleaving strategy can be further extended to other switching frequency range and other multi-channel interleaved PFC.

This paper proposes a novel synchronous rectifier driving scheme for resonant converters. An LLC resonant converter with proposed synchronous rectification is designed and analyzed. It is a high efficiency, high power density solution for future frond end converters. Hold up time extension capability is achieved for designed LLC resonant converter without sacrificing the efficiency for nominal condition. 1kW, 1MHz LLC resonant converter with proposed SR is built to demonstrate its advantages (size and efficiency) over the diode rectification and PWM converter. Overall 95.1% efficiency and 96W/in 3 power density are achieved.

Bulky holdup time capacitor prevents further increasing power density of front-end AC/DC converters. Instead of using auxiliary circuits, a high frequency isolated dual boost converter is proposed to reduce holdup time capacitor. ZVS can be achieved for both primary side and secondary side switches. Moreover, low voltage stress on the secondary side devices and simple synchronous rectification control make the topology attractive for low output voltage applications. The converter operates optimally under normal condition with wide input voltage range. Based on theoretical analysis, the proposed converter can reduce holdup time capacitor from 1000uF to 440uF with 1200W output power.

Remarkable progresses have been made over the past decade in power conversion technologies, including advanced power semiconductor devices, power management ICs, innovative circuit topologies, and packaging and integrated system solutions. These technological advancements have been manifested in a wide range of products and applications with ever increasing performances, efficiency, and power density. This paper highlights some of the challenges and opportunities of power conversion technologies in the distributed power system (DPS) for computer, telecommunication and network products. Topics discussed in this paper include improved EMI filter design techniques to mitigate the detrimental effects of filter-converter parasitics; impacts of the operating frequency of PFC to the size and weight of EMI filter; power conversion architecture and potential simplification; high-frequency high-density AC/DC and DC/DC topologies and designs; bus converters; as well as non-isolated point- of-load converters

Hybrid solid oxide fuel cell (SOFC)-gas turbine (GT) power system provides a promising solution for powering the future aircraft. This electrical power generation technology can achieve both the high efficiency and very low emission. However, two independent energy sources in the system, SOFC and GT, require more dedicated power management strategy. A novel power tracking control method is proposed in this paper to address the issue of power partitioning between two energy sources. In order to analysis and verify the control strategy in the hybrid SOFC system, a detailed system simulation platform is developed. The simulation results demonstrate that the power tracking control can effectively control the load power distribution between two channels.

In this paper, the power factor concept of resonant converters is proposed and analyzed. A novel constant power factor control scheme for high-frequency high-power-density charging applications is proposed and studied. Based on this control scheme, the circulating energy of resonant converters is considerably reduced. Low switching losses are also achieved with very low turn off current. High efficiency can be obtained for high-frequency high-power (several kilowatts) charging applications. A 700 kHz, 10 kV three-level LCC resonant converter is designed to validate the proposed control scheme. The power density of 50W/inch/sup 3/ is achieved with over 88% efficiency at full load.

Although LLC resonant converter can achieve wide operation range with high efficiency, lack of design methodology makes it difficult to be implemented. In this paper, based on the theoretical analysis on the operation principles during normal condition and holdup time, the relationship between converter efficiency and operation range with different circuit parameters has be revealed. An optimal design methodology has been developed based on the revealed relationship. A 1MHz, 1kW LLC converter is designed to verify the proposed method.

In this paper, a high-density high-voltage distributed power system for pulse power applications is designed and implemented. Different topologies are evaluated for two power stages. According to pulse load condition, system power density is optimized through the tradeoff between power loss and magnetic component size. High power density and high efficiency are verified by the experimental result.

This paper introduces a high power-density, high-efficiency isolated full-bridge boost converter, which is used for the front-end converter of a capacitor charger. The design equations, design considerations and practical trade-offs for the converter power stage are summarized. In addition, by fully taking advantage of the pulsed load profile, a transformer design using a high-saturation flux density material is introduced to maximize the power density. The principle of operation for the converter is analyzed and verified on a 15 kW, 100 kHz front-end converter prototype.

A Si CoolMOS FET and SiC diode assembly with gate driver in boost configuration (ratings at 600 V/12 A), for power factor correction (PFC) application, has been fabricated in a version of IPEM - integrated power electronics module. It uses technology of so-called embedded power (EP), to form a three-dimensional (3-D) multiple chips/components interconnection with the capability of functional integration and high performance. An integrated power chip stage is built by embedding chips in a co-planar ceramic substrate and building up onto it a metallization thin-film interconnection. This deposited metallization not only bonds the power chips, but also provides the second-level interconnect wiring, so that associated components and base substrate are mounted from top and bottom sides. In this paper, the switching parameters of this module and their effects on a converter's performance have been experimentally characterized. The procedures adopted for the defined fabrication processes of planar metallization interconnecting and solder stacking, are presented. In addition to the improvement of structural electrical properties, compared to a conventional discrete version, the characteristics of the planar process integration have also been demonstrated.

For paralleling DC/DC converters, this paper investigates the fundamental relationship between the outer-loop current sharing control and the voltage regulation control. By using the concept of output impedance, the inherent function of the current sharing control is clarified and its influences on the voltage regulation of paralleling system are revealed. Although there may exist tradeoffs between dynamic current sharing and voltage regulation, it is possible to have good performances on both aspects, as long as the closed-loop output impedances of individual modules are within a certain tolerance range. After that, a design guideline for the current sharing compensator is proposed. The analyses and designs are verified by the simulation and experimental results.

The LLC resonant converter has some special characteristics to make it an excellent candidate for front-end DC/DC conversion in a distributed power system. Even with advanced topology, to achieve high power density, the passive component design is still the key issue. Passive integration is used to integrate all the passive components within the resonant tank of the LLC resonant converter into one single component - an integrated L-L-C-T. The design approach and loss estimation of the integrated L-L-C-T component for a 1 MHz 1 kW LLC resonant converter is given in this paper. A prototype is constructed and tested under small signal and in-circuit working conditions.

For high-voltage charging applications, this paper introduces a variable-frequency zero-voltage-switching three-level LCC resonant converter, which is able to utilize the parasitic components of the high-turns-ratio transformer. By applying the three-level structure in the primary side, low-voltage MOSFETs can be used to minimize the conduction loss. Therefore, the switching frequency can be increased to shrink the size of passive components. In addition, a simulation-based process is presented for designing the resonant-tank parameters as a trade-off among the efficiency, power density and component stresses. The principle of operation for the converter is analyzed and verified on a 3 kW, 200 kHz, 10 kV charger prototype.

This paper presents a digital controller for boost power factor correction (PFC) converter. The digital controller features an optimal digital current compensator and a novel current-loop feed-forward (CFF) compensation. The CFF compensation can improve power factor without increasing the current-loop gain and bandwidth. Experiment results are shown to validate the design approach.

Assemblies of power semiconductor switches achieved to some extent, the number of interconnects and their associated drive circuit are at present available in modules. Upward into the multikilowatt range, mixed mode module construction is used. This incorporates monolithic, hybrid, surface mount and wirebond technology. However, a close examination of the applications in motor drives and power supplies indicates that there has been no dramatic volume reduction of the subsystem. The power semiconductor modules have shrunk the power switching part of the converter, but the bulk of the subsystem volume still comprises the associated control, sensing, electromagnetic power passives (inductors, transformers, capacitors) and interconnects. This paper addresses the improvement of power processing technology through advanced integration of power electronics. The goal of a subsystem in a module necessitates this advanced integration, incorporating active switching stages, EMI-filters and electromagnetic power passives into modules. The central philosophy of the technology development research in the National Science Foundation Engineering Research Center for power electronic systems is to advance the state of the art by providing the concept of integrated power electronics modules (IPEMs) for all these functions. The technology underpinning such an IPEM approach is discussed. The fundamental functions in electronic power processing, the materials, processes and integration approaches and future concepts are explained

To achieve higher power density, power converters are operating at higher switching frequencies. For the high switching frequency operating, not only the efficiency, but also the EMI performance is a big concern. In this paper, based on the developed EMI noise model, switching frequency impact on the single-switch CCM PFC is analyzed and evaluated. Switching frequency selection guideline is given.

The wide application of the power factor correction (PFC) techniques in the distributed power system (DPS) and the stringent international standards make it necessary to understand and predict the conducted electromagnetic interference (EMI) of the PFC circuit. Time domain simulation plus fast Fourier transform (FFT) is a viable method. However, the simulation circuit has to be carefully modeled, and must cover high frequency characteristics up to 30 MHz. For this purpose, multiple modeling and characterization techniques in the medium and high frequencies are developed, which finally lead to a good simulation circuit in Saber for a 1 KW continuous-conduction-mode (CCM) PFC converter. The conducted EMI of the PFC converter has been successfully predicted up to 30 MHz in terms of both differential-mode (DM) and common-mode (CM) noise, which substantiates the afore-mentioned modeling and characterization techniques. To explain the conducted EMI behavior of the CCM PFC in a systematic way, the DM and CM loop models of PFC EMI are proposed for describing the noise generation and propagation mechanisms. The effects of the PFC inductor and the parasitic capacitances at the MOSFET drain node are investigated to verify the validity of the DM and CM loop models.