The paper deals with the properties of silicon films obtained by low-pressure chemical vapour deposition (LPCVD). Two gaseous sources characterized by different deposition temperatures, i.e. disilane S12H6 (420-520 degrees C) and silane SiH4 (520-750 degrees C), was studied in order to understand the influences of deposition and crystallization kinetics on silicon film properties. Thus, the deposition of amorphous, semi-crystallized and polycrystalline silicon films was related to "volume random" and "surface columnar" crystallization phenomena, highlighting a linear relationship between the refractive index and the polysilicon volume fraction and, showing complex residual stress dependency with process conditions. Finally, by introducing the ratio V-d/V-c between the deposition and crystallization rates as a major parameter, different deposition behaviours and related semi-empirical relationships were defined in order to characterize fully the various properties of LPCVD silicon films (microstructure, polysilicon volume fraction, refractive index and residual stress) according to the chosen gaseous source, silane or disilane. (C) 2010 Elsevier B.V. All rights reserved.

This work addresses electric charge measurement in gate oxides of metal-oxide-semiconductor (MOS) structures submitted to dc stress similar to that applied in power electronics components during service (2 MV/cm to 4 MV/cm). The qualitative and quantitative variation of the charge is analyzed via capacitance-voltage and thermal-step measurements, taking into account the structure geometry and the different phenomena occurring during stress.It is shown that, while the capacitance-voltage technique, which is mainly sensitive to the charges placed near the substrate, the thermal-step method is more sensitive for detecting the charges placed all over the oxide. It is shown that the association of the two complimentary techniques can allow to identify and to localize the charges across the quasi-totality of the gate oxide.

Silicon oxynitride films were deposited by plasma-enhanced chemical vapor deposition at low temperature and frequency using SiH4 + NH3 + N2O gas mixtures. The process is optimized in order to deposit film with low tensile stress and high resistance during KOH etching. By increasing the gas flow of nitrous oxide (N2O), the film tends to be oxygen rich and the usual as-deposited high compressive stress is reduced to its lowest state at O/Si = 0.74. Annealing films above 480 degrees C generates low tensile stress suitable for membrane fabrication, and further infrared spectroscopy analysis shows that the shrinking of Si-O and Si-N bonds seems to be the cause of reversing the stress's nature. Young's modulus of the optimized layer is characterized by indentation. In application, 75 Omega coplanar waveguides (CPW) were fabricated on the top of an oxynitride membrane and characterized in term of insertion loss and effective permittivity. The results were compared to those obtained with the well-controlled bilayer silicon oxide-nitride membrane technology. The obtained losses are lower than 0.2 dB at 30 GHz with a free-space propagation signal.

This work is concerned with the development of a non destructive method for measuring electric charge in metal-oxide-semiconductor (MOS) components and devices. The aim is to obtain further information on microelectronics and power electronics components and, using the gate oxide state, to assess semiconductors health. Results obtained on MOS samples with oxide thicknesses of 2 nm, 50 nm and 120 nm, and on power electronics modules are presented.

One of the steps of the power components reliability improvement is to integrate protection structures (Robb, 1994 and Yeki, 1994). An integrated structure which protect IGBT against short-circuit conditions has already been studied. This structure has been studied and improved for its integration in a classical IGBT technological process (Caramel, 2006). Generally, the integration of protection structures and power devices on the same substrate leads to insulation problems. In order to overcome these problems for our application, we propose in these paper three insulation techniques compatible with a classical IGBT technological process. [2D] numerical simulations have been thus performed in order to highlight the necessity of insulation and for compare the insulation techniques efficiency

P+ walls through wafer can be considered as key regions in the 3D architecture of new bi-directional current and voltage power integrated devices. Moreover, these P+ walls can be used as electrical vias in the design of microsystems, in order to make easier 3D packaging. In this paper, we demonstrate the possibility of fabricating these P+ walls combining the deep RIE of silicon and deposit of boron-doped polysilicon.

This work concerns the use of the thermal step method (TSM) for measuring electric charge in metal-oxyde-semiconductor (MOS) structures used in micro and nano-electronics, The TSM is a non destructive method for quantifying and localizing the electric charge in solid insulating materials and structures. Its principle is the application of a low thermal step to a short-circuited or dc-biased sample and the analysis of a current response, which depends on the charge present in the device. An adaptation of the technique (so far used in thick insulating materials and structures for electrical engineering) to short-circuited and biased MOS devices, is described. Results obtained on biased MOS structures and their correlation with classical capacitance-voltage (C-V) measurements are given. Estimations, by the TSM, of the amount of charge trapped in the oxide and. of the space charge penetration depth in the silicon substrate are presented.

Nitrogen doped silicon films have been deposited by low pressure chemical vapour deposition from disilane Si2H6 and ammonia NH3. Deposition kinetics is investigated, pointing out the influences of the deposition temperature, the total pressure and the gas flow rates. According to the Bruggeman theory, variations of the NH3/Si2H6 gaseous ratio allow for a wide range of the SiNx stoichiometry as well as a good control of the film nitrogen doping. The different behaviours of the nitrogen atom in silicon films are discussed and an overview of the nitrogen doped silicon physical properties (optical, mechanical and electrical) is proposed for the development of boron-doped polysilicon gates.

The capacitance-voltage measurement (C-V), performed at frequencies higher than 10 kHz, has been so far the most used technique for measuring the charges present in Metal-Oxide-Semiconductor (MOS) structures. The C-V measurement allows to estimate the total amount of charge trapped within the SiO/sub 2/ layer which constitutes the insulator of the structure, but do not provide information about the charge distribution. The question if all the carriers trapped in the MOS structure are detected by C-V can also be asked. The aim of this work is to study the use of a method for space charge localization in insulating materials, namely the thermal step method (TSM), for characterizing MOS structures. The TSM has been adapted and applied to the short-circuited and biased MOS devices. A non irradiated and an irradiated MOS capacitor comprising a 100 nm thick SiO/sub 2/ layer are studied. The three operating modes of such devices under positive and negative bias (accumulation, depletion and inversion) are put into evidence, and the threshold voltage, which is affected by the space charge trapped in the oxide, is measured precisely. The results obtained by TSM, corresponding to measurement frequencies lower than 1 Hz, appear to be highly correlated with the C-V measurements, and seem to present a significant sensitivity. Estimations, by TSM, of the amount of charge trapped in the oxide and of the space charge penetration depth in the Si layer are presented.

Various silicon rich silicon nitride SiNx films have been deposited by low-pressure chemical vapour deposition (LPCVD) from dichlorosilane SiH2Cl2 and ammonia NH3. Deposition rate, refractive index, residual stress and SiNx stoichiometry are studied as a function of deposition parameters, evidencing the main influence of the NH3/SiH2Cl2 gas ratio. However, as such SiNx layers have special applications for micro-opto-electromechanical systems (MOEMS), the influences of the deposition conditions are more precisely studied for improving the uniformity properties along the load. In order to achieve this goal, different load configurations are tested and the use of non-isothermal furnace profiles is proposed in order to develop the LPCVD deposition technique of SiNx films for industrial microtechnological processes.

An e-beam nanolithography process with metal lift-off is optimized to produce four-electrode co-planar metal-insulator-metal nanojunctions with an inter-electrode distance down to 10 nm. The e-beam exposure technique is simulated to find the best geometry of the four electrodes. The fabrication process is presented and compared in detail with the simulation. AFM images of four-electrode nanojunctions down to 10 nm are presented. These nanojunctions are well adapted to interconnect hybrid molecular electronic devices.

In this paper, a flexible technological process suitable for the development of complex integrated power structures based on the functional integration mode is presented. This technological process is based on a succession of basic technological steps corresponding to the fabrication of IGBT devices and compatible specific steps supporting more complex functions

An optimised process is presented to fabricate co-planar metal-insulator-metal nanojunctions down to an inter-electrode distance of 5 nm. Simulation of the e-beam insulation of the PMMA/SiO2/Si interface is used to optimise the PMMA resist thickness and the exposure strategy. The process was well stabilised to provide a full statistical analysis of the number of nanojunctions produced per wafer. A 10% throughput was reached for 5 nm giving a mass production of about 100 nanojunctions per 2 inches wafer all equipped with their interconnection pads.

Planar metal/semiconductor/metal (PMSM) junctions buried in a SiO2 layer are fabricated using electron beam lithography on a silicon sample. A technique of jump of pixels is used to obtain different sizes of junctions, the smallest having an inter-electrode distance of 5 nm. The current-voltage characteristics and the variation of the junction conductance with the temperature down to 8 K have been studied. At all sizes and for both polarities, the I-V curves correspond to the reverse characteristic of a metal/semiconductor contact. At low bias voltage, the influence of a thin insulator interfacial layer between the metal and the semiconductor has been pointed out. For these junctions, a non-linear low voltage I-V characteristics is observed before the large voltage thermionic emission regime. For the smallest junctions obtained without interfacial oxide layer, a linear I-V characteristic is recovered at low voltage. Their conductance can be lowered by decreasing the temperature.

In this paper, amorphous, semi-crystalline and polycrystalline silicon films have been deposited by low pressure chemical vapour deposition (LPCVD) from silane SiH4 by ranging the deposition temperature from 555 to 635°C and the total pressure from 100 to 300 millitorrs. Films residual stresses have been determined thanks to the formula of Stoney by measurements of the wafer curvature before and after removal of the back side deposition. The influences of the different deposition parameters are reported and major stress variations are evidenced. By studying the effects of a 600°C crystallisation anneal and by comparing them to those observed for amorphous silicon films deposited from disilane Si2H6, compressive and tensile stresses are respectively related to “surface” and “volume” crystallisation phenomena. The different stress values of amorphous and polycrystalline silicon have been estimated and, according to these results, solutions are finally proposed in order to have a real control of residual stress into silicon depositions and to obtain low stress (s ≈ 0) polysilicon films.

To measure the electrical resistance of a single molecule, one way is to connect it between two coplanar metallic electrodes. Our choice is to bury the metallic electrodes in the insulating SiO2 layer, on top of a silicon substrate. Nanojunctions lower than 10 nm have been fabricated by using electron beam lithography and AuPd lift-off. SiO2 at the same height as the metal enables us to explore the junction surface between the electrodes using an AFM. Another advantage of such device is the possibility to use the bulk silicon under the surface to "short-circuit" the nanojunction at room temperature. There are many different transport regimes through a Metal-Silicon-Metal (M-Si-M) junction depending on its size (thermionic, avalanche,..). This was used to establish that the current is localized through the nanojunction at low temperature. This makes the M-Si-M device modulable with temperature ready for the deposition of a single molecule.

A process is presented to fabricate a coplanar buried metal - - metal junction on the surface. The surface is etched with reactive ion etching (RIE) through a PMMA mask where the junction patterns have been defined using the e-beam technique. The buried AuPd metallic wires of the junction, 200 nm in width and 10 nm in thickness, are fabricated by the lift-off technique. After the RIE step, the difficulties of reaching an electrode separation in the 40 nm range on are also discussed.

We have studied the use of spin-on glass (SOG), as a sacrificial layer and source of dopant, for the realization of an electrostatic micromotor. Some difficulties have been encountered, and we propose a new process based on SOG, a classical POCl3 dopant source and oxidation of polysilicon to avoid these difficulties.

An improvement of a process to fabricate co-planar metal-insulator-metal nanojunctions is presented to reach a gap length much lower than 10 nm using a 20 keV e-beam and an AuPd lift-off. The electrodes of the nanojunction are less than 100 nm in width and are buried in the SiO2 substrate. For the 8 nm nanojunctions, the gap is still filled with SiO2 if care is taken about the SiO2 etching step of the process.

The results of a nanolithography process for making co-planar tunnel junctions with a gap length lower than 30 nm and electrode width in the 100 nm range are presented. These electrodes are buried in the SiO2 substrate which makes the SiO2 gap surface accessible for atomic force microscopy characterization.