FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge in designing FPGA-based systems is partitioning computation between processor cores and FPGAs. An appropriate division of labor is difficult to predict in advance and requires experiments and measurements. When an investigation requires rewriting part of the system in a new language or with a new programming model, its high cost can delay design-space exploration. A single-language system with an appropriate programming model and compiler that targets both platforms transforms this tedious exploration to a simple recompile with new compiler directives. This work introduces StreamBlocks, a unified open-source software/FPGA compiler and runtime that takes dataflow programs written in Cal, and automatically partitions them across heterogeneous CPU/FPGA platforms. The explicit task-parallel semantics of dataflow allows our compiler to simultaneously take advantage of thread parallelism on software and spatial parallelism on hardware. StreamBlocks is augmented with a profile-guided auto-partitioning tool that helps identify the best hardware-software partitions. We demonstrate the capability of our compiler in finding the right balance between hardware and software execution on both a high-end datacenter accelerator card and an embedded board. Our experiments exhibit a 4 -- 7× speedup over trivial partitions. This speedup is achieved automatically with zero code modifications.

To increase performance and efficiency, systems use FPGAs as reconfigurable accelerators. A key challenge in designing these systems is partitioning computation between processors and an FPGA. An appropriate division of labor may be difficult to predict in advance and require experiments and measurements. When an investigation requires rewriting part of the system in a new language or with a new programming model, its high cost can retard the study of different configurations. A single-language system with an appropriate programming model and compiler that targets both platforms simplifies this exploration to a simple recompile with new compiler directives. This work introduces StreamBlocks, an open-source compiler and runtime that uses the CAL dataflow programming language to partition computations across heterogeneous (CPU/accelerator) platforms. Because of the dataflow model's semantics and the CAL language, StreamBlocks can exploit both thread parallelism in multi-core CPUs and the inherent parallelism of FPGAs. StreamBlocks supports exploring the design space with a profile-guided tool that helps identify the best hardware-software partitions.

This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow description of an algorithm as input and generates a combination of hardware (in Chisel) and software (in C) that interacts with the hardware. The hardware can be integrated with RISC-V cores created by the Rocket Chip generator and the software can be executed on these cores.The generated hardware requires similar amount of resources as the hand-written hardware while achieving equal or higher clock rates. As expected, the accelerators perform the calculations faster than the general purpose processor, 5 to 33x in our experiments. When these accelerators are integrated with the Rocket cores, they increase the performance by 25% and 260% in the two use-cases we investigate.

Hardware-software codesign for FPGAs requires flexible and changeable boundaries between hardware and software. Design space exploration is facilitated by expressing programs in a language that can be compiled for both CPU and FPGA execution. Such an approach requires efficient and general communication mechanisms between hardware and software. We present a practical solution to this problem for heterogeneous programs expressed in CAL, an actor based language running on a PCIe-based FPGA system where communication between a processor and FPGA is relatively expensive. We show how a network of continuously executing software and hardware actors with fine-grained communication can be expressed as a coprocessor model that executes the network in discrete steps with efficient coarse-grained transfers across the PCIe bus. To this end, we present the Triggered Scheduling (TS) algorithm to detect idleness (i.e. lack of forward progress) of a dynamic actor network with unpredictable consumption/production rates. With TS, it is possible to treat a network of actors running on hardware as a coprocessor that can be called by software. We show how TS can be used to build a truly heterogeneous system on a HLS platform. Using 4 large benchmarks, we analyze the performance and resource utilization of the Triggered Scheduling algorithm.

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently specify and explore the design space of applications executing on the different components of heterogeneous platforms remains an open problem and is the subject of many research efforts. The paper describes a dataflow based approach for the synthesis of applications to be executed on mixed CPU and GPU architectures. The new high-level approach consists of partitioning the application dataflow program written in RVC-CAL into CPU and GPU components, then on generating by automatic synthesis the C++ and CUDA programs that together implement the application executable. The design approach provides portability of applications on CPUs, GPUs, and mixed CPU/GPU architectures as well as the possibility of exploring the design space of all partitioning options without the need of rewriting the application code. The paper describes the essential methodology features at the base of the synthesis of CPU/GPU code and reports some example design cases validating the correctness of the approach.

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resources, pipelining optimization without (or with minimal) resource sharing can give significant advantages in performance. High-level synthesis of CAL-programs is particularly popular in computation intensive applications (e.g., image and video processing, cryptography, wireless communication, etc.) where feedback actors with data flows at input and output ports represent loop-like behavior. In this work, we propose techniques for transforming, analysis, speculatively pipelining and optimizing large branched feedback dataflow programs. We develop an accurate algorithm and introduce fast dynamic and mixed static / dynamic heuristics that firstly minimize the number of pipeline stages for a given pipeline-stage time-period, and secondly minimize the overall pipeline registers size by means of appropriate assignment of feedbacks and instructions to pipeline stages. We also propose a genetic algorithm for tuning the heuristics for a particular design. The experimental results show the algorithms we propose give quickly solutions that are very close to accurate solutions and overcomes the earlier developed algorithms regarding computing time and pipeline parameters.

The use of parallelism has increased drastically in recent years. Parallel platforms come in many forms: multi-core processors, embedded hybrid solutions such as multi-processor system-on-chip with reconfigurable logic, and cloud datacenters with multi-core and reconfigurable logic. These heterogeneous platforms can offer massive parallelism, but it can be difficult to exploit, particularly when combining solutions constructed with multiple architectures. To program a heterogeneous platform, a developer must master different programming languages, tools, and APIs to program each aspect of platform separately and then must find a means to connect them with communication interfaces. The motivation of this work is to provide a single programming model and framework for hardware-software stream programs on heterogeneous platforms. Our framework, StreamBlocks, starts with a dataflow programming model for both embedded and datacenter platforms. Dataflow programming is an alternative model of computation that captures both data and task parallelism. We describe a compiler infrastructure for CAL dataflow programs for hardware code generation. CAL is a dataflow programming language that can express multiple dataflow models of computation. StreamBlocks is based on the Tycho compiler infrastructure, which transforms each actor in a dataflow program to an abstract machine model, called Actor Machine. Actor Machines provides a unified model for executing actors in both hardware and software and permit our compiler extension and backend to generate efficient FPGA code. Unlike other systems, the programming model and compiler directly support hardware-software systems in which an FPGA functions as a coprocessor to a CPU. This permits easy integration with existing workflows.

This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming language for the memory processing of data tokens. It does not require essential changes to the model of computation (MOC) or to the dataflow program itself. The objective of the approach is to remove the unnecessary constraints of memory isolations without introducing limitations to the scalability and composability properties of the dataflow paradigm. Thus the identified optimizations allow to keep the same design and programming philosophy of dataflow, whereas aiming at improving the performance of the specific configuration implementation. The different optimizations can be integrated into the current RVC-CAL design flows and synthesis tools and can be applied to different sub-networks partitions of the dataflow program. The paper introduces the context, the definition of the optimization problem and describes how it can be applied to dataflow designs. Some examples of the optimizations are provided.

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such platforms require to the designer either to modify the software or hardware based designs to obtain higher performance implementations. Thus, the developer needs to either rewrite functional blocks in HDL or to use high-level synthesis of C-like sequential languages with platform locked extensions. In this paper, a compiler infrastructure that takes as input a single behavioral representation, expressed in high-level dataflow RVC-CAL language, is proposed for programming any of the components of heterogeneous Zynq MPSoCs platforms without the need of modifying any line of code on the design.

The latest wave of connected digital systems, nowadays called Internet of Things (IoT) promises various gains, especially in terms of significant ease of data access. A large number of different platforms for IoT applications, however, makes their development difficult and time-consuming leading to projects that are failed to be on time, on budget or fully completed. To address the platform heterogeneity, this paper presents the ongoing work on development environment called Orcc-IoT. Orcc-IoT facilitates the development of IoT by combining dataflow modelling language, heterogeneous code generator and the library of ready-made IoT actors. The utilisation of Orcc-IoT in development is expected to increase the quality, and to reduce the development costs and time-to-market of IoT applications.

The rapid detection and identification of infectious pathogens are a critical need for healthcare in both developed and developing countries. There is a need for portable diagnostics and epidemiological surveillance systems that can be deployed in remote field settings for infectious diseases testing, such as pandemic "hotspots" in Africa or southeast Asia. Together with the Vital-IT and Swiss-Prot groups, we developed a fast pathogen detection embedded hardware accelerator (no bigger than 75x50mm) capable of analyzing up to 250Mnt/s of DNA sequence. To deploy this solution, an embedded DNA Next Generation Sequencer (NGS) is used for retrieving the genetic material from patients sample at the point of care (e.g., the Oxford Nanopore Technologies MinION). Successively, the collected DNA sequences are analized in order to detect the presence of known pathogen patterns. Currently, up to 100 different pathogens can be analized at the same time using one single embedded accelerator. Due to the low-power consumption of this hardware accelerator, it is possible to give access to worldwide health organizations and local administrations to a complete real-time embedded and battery powered surveillance solution. Moreover, this solution can greatly scale to big computing clusters, where a larger pathogens number can be analized in parallel, outperforming current state of art computationally expensive solutions.

The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given optimization functions in terms of throughput, memory usage, and energy consumption. This problem is NP-hard even for two cores. Thus, finding a close-to-optimal solution consists of exploring the design space by appropriate heuristics identifying those design points that maximize or minimize the desired (multiple) objective functions subject to a set of constraints. In general, exploring the design space efficiently is a challenging task due to the massive number of admissible design points. Efficient estimation methodologies are necessary to support an effective search of the design space by reducing to a minimum the cost and the number of measurements on the physical platform. This paper presents a new methodology that provides high-precision estimations of dynamic dataflow programs performances on multi/many-core platforms for any set of design configurations. The estimations rely on the execution trace post-processing obtained by a single profiled execution of the program. Furthermore, the paper describes the estimation methodology, implementation tools, and the type of information that is obtained from many/multi-core dataflow executions and used to drive the optimization heuristics. The results confirm a high level of accuracy achieved on different types of platforms and the effectiveness of the illustrated design space exploration methodology.

This paper presents shared-variable synchronization approaches for dataflow programming. The mechanisms do not require any substantial model of computation (MoC) modification, and is portable across both for hardware (HW) and software (SW) low-level code synthesis. With the shared-variable formalization, the benefits of the dataflow MoC are maintained, however the space and energy efficiency of an application can be significantly improved. The approach targets Dynamic Process Network (DPN) dataflow applications, thus making them also suitable for less expressive models e. g. synchronous and cyclostatic dataflow that DPN subsumes. The approach is validated through the analysis and optimization of a High-Efficiency Video Coding (HEVC) decoder implemented in the RVC-CAL dataflow language targeting a multi-core platform. Experimental results show how, starting from an initial design that does not use the shared-variable formalism, frames per second throughput performance is increased by a factor of 21.

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resources, pipelining optimization without resource sharing can give significant advantages in performance. In this work, we propose a novel pipeline optimization heuristic algorithm, which is named HADD. It is suitable for very large dataflow programs and makes use of efficient dynamic heuristics and a random search on the set of solutions. For a pipeline-stage time-period, it quickly minimizes the number of stages and successively finds the assignment of operators to stages with the objective of minimizing the overall pipeline registers size. The experimental results show that HADD gives solutions that are very close to accurate solutions with only 2% of the difference and overcomes by about 10% on average the best-known heuristic technique HT, which uses mixed static-dynamic heuristics on large designs. Moreover, HADD is c. a. 10 times faster on average against HT.

The paper presents the results of design space explorations for the implementation of the Smith-Waterman (S-W) algorithm performing DNA and protein sequences alignment. Both design explorations studies and FPGA implementations are obtained by developing a dynamic dataflow program implementing the algorithm and by direct high-level synthesis (HLS) to FPGA HDL. The main feature of the obtained implementation is a low-latency, pipelinable multistage processing element (PE), providing a substantial decrease in resource utilization and increase in computation throughput when compared to state of the art solutions. The implementation solution is also fully scalable and can be efficiently reconfigured according to the DNA sequence sizes and performance requirements of the system architecture. The implementation solution presented in the paper can efficiently scale up to 250MHz obtaining 14746 Alignments/s using a single S-W core with 4 PEs, and up to 31.8 Mega-Alignments/min using 36 S-W cores on the same FPGA for sequences of 160×100 nucleotides.

This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing, packet processing, etc. This paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of at-size applications synthesized on field-programmable gate arrays platforms demonstrate power reductions achievable with no loss in data throughput.

This paper describes a profiling methodology and its implementation applied to dynamic dataflow programs running on embedded heterogeneous platforms. Starting from an high-level and platform independent representation of the program, the approach automatically generates low-level platform-specific source code including specific profiling capabilities. Profiling information is then collected during the profiling execution and successively used during the design space exploration stages. The methodology has been developed and validated using different application design based on dynamic dataflow program implementations running on a multi-core ARM MPSoC architecture.

The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by writing a dynamic dataflow program implementing the algorithm and by direct high-level synthesis (HLS) to FPGA HDL. The main feature of the obtained implementation is a low-latency, pipelinable multistage processing element (PE), providing a substantial decrease in the resource utilization and an increase in the computation throughput when compared to state of the art solutions. The implementation solution is also fully scalable and can be efficiently reconfigured according to the DNA sequence sizes and to system performance requirements. The FPGA design presented in the paper can efficiently scale up to 250 MHz obtaining 14746 Alignments/s using a single S-W core with 4 PEs, and up to 31.8 Mega-Alignments/min using 36 S-W cores on the same FPGA for sequences of 160x100 nucleotides.