Abstract Oxide-based memristors are promising candidates as neuromorphic hardware in energy-efficient edge computing applications for the Internet of Things (IoT). However, achieving simultaneously optimized memristive and synaptic performance with low-temperature fabrication, compatible with complementary metal-oxide-semiconductor (CMOS) processes, remains a challenge. Here, we demonstrate a dual-function electrode selection strategy—controlled oxygen vacancy electrode reservoir—implemented in a simple, low-temperature-fabricated indium tin oxide (ITO)/WO3/TiN thin film system. We systematically vary the oxygen stoichiometry in the ITO top electrode, which serves not only as an electrical contact, but also as a dynamic oxygen reservoir. A high oxygen-vacancy concentration in the ITO enables optimized memristive performance of low electroforming and operation voltages, and robust memristive and synaptic endurance. This electrode-focused defect engineering approach offers a versatile route to advanced memristor design, enabling many applications in IoT and neuromorphic systems.

Zeroth-order (ZO) optimization estimates gradients using only forward-pass evaluations, making it suitable for fine-tuning non-differentiable, event-driven spiking neural networks (SNNs). However, its deployment on in-memory computing (IMC) accelerators is constrained by the repeated read-modify-write (RMW) operations arising from explicit weight perturbation and the prohibitive hardware footprint of random number generators (RNGs) for statistically independent per-weight perturbations. To address these challenges, we propose an implicit-perturbation ZO (IPZO) architecture in which perturbation sums computed by an event-triggered perturbation generation unit (PGU) are combined with the weighted sums produced by the IMC array, eliminating perturbation-induced RMW operations while preserving weight-stationary execution of IMC. By exploiting spike sparsity, the PGU generates and accumulates perturbation contributions only for spike-activated weight rows, reducing the required row dimension of the RNG array. An address-driven XOR recombination scheme (PGU-XOR) is further introduced to mitigate the spatial correlations caused by direct RNG reuse (PGU-Reuse). The results show that (1) PGU-XOR matches software RNGs in accuracy on Spikingformer/CIFAR-10 (76.41

Neuromorphic and quantum computing have recently emerged as promising paradigms for advancing artificial intelligence, each offering complementary strengths. Neuromorphic systems built on spiking neurons excel at processing time-series data efficiently through sparse, event-driven computation, consuming energy only upon input events. Quantum computing, on the other hand, leverages superposition and entanglement to explore feature spaces that are exponentially large in the number of qubits. Hybrid approaches combining these paradigms have begun to show potential, but existing quantum spiking models have important limitations. Notably, prior quantum spiking neuron implementations rely on classical memory mechanisms on single qubits, requiring repeated measurements to estimate firing probabilities, and they use conventional backpropagation on classical simulators for training. Here we propose a stochastic quantum spiking (SQS) neuron model that addresses these challenges. The SQS neuron uses multi-qubit quantum circuits to realize a spiking unit with internal quantum memory, enabling event-driven probabilistic spike generation in a single shot. Furthermore, we outline how networks of SQS neurons – dubbed SQS neural networks (SQSNNs) – can be trained via a hardware-friendly local learning rule, eliminating the need for global classical backpropagation. The proposed SQSNN model fuses the time-series efficiency of neuromorphic computing with the exponentially large inner state space of quantum computing, paving the way for quantum spiking neural networks that are modular, scalable, and trainable on quantum hardware.

Emerging edge intelligence systems increasingly rely on dense deployments of always-on sensors that must convey task-relevant information to a remote model under tight energy and spectral budgets. The deployment of event-driven neuromorphic sensing paired with spiking neural networks (SNNs) is attractive in this regime because it produces dynamically sparse representations, so that energy is spent on communication and computation only when informative events occur. Prior multiple-access protocols for remote inference using neuromorphic sensing and computing targeted collaborative settings, in which the server fuses information from all devices into a single decision. This paper instead addresses parallel remote inference, in which each device observes a distinct input, and requires its own classification decision. We propose NOMA-NC, a non-orthogonal multiple-access (NOMA) neuromorphic communication (NC) protocol built on the vector symbolic architecture (VSA) framework. In NOMA-NC, each device binds its sparse spike feature map with a device-specific permutation key, and all devices in a group transmit concurrently so that the over-the-air superposition directly realizes the VSA bundling operation. A shared decoding SNN, together with lightweight per-device learned unbinding, recovers all decisions in a single inference pass. Experiments on the N-MNIST and DVS128 Gesture datasets show that NOMA-NC yields goodput gains and savings in terms of receiver computing energy that are sub-proportional to the number of simultaneously active devices, without increasing the per-device transmission energy.

Analog in-memory computing (AIMC) offers a promising solution to the von Neumann bottleneck. However, deploying transformer models on AIMC remains challenging due to their inherent need for flexibility and adaptability across diverse tasks. For the benefits of AIMC to be fully realized, weights of static vector-matrix multiplications must be mapped and programmed to analog devices in a weight-stationary manner. This poses two challenges for adapting a base network to hardware and downstream tasks: (i) conventional analog hardware-aware (AHWA) training requires retraining the entire model, and (ii) reprogramming analog devices is both time- and energy-intensive. To address these issues, we propose AHWA low-rank adaptation (AHWA-LoRA) training, a novel approach for efficiently adapting transformers to AIMC hardware. AHWA-LoRA training keeps the analog weights fixed as meta-weights and introduces lightweight external LoRA modules for both hardware and task adaptation. We validate AHWA-LoRA training on SQuAD v1.1 and the GLUE benchmark, demonstrate its scalability to larger models, and show its effectiveness in instruction tuning and reinforcement learning. We further evaluate a practical deployment scenario that balances AIMC tile latency with digital LoRA processing using optimized pipeline strategies, with RISC-V-based programmable multi-core accelerators. This hybrid architecture achieves efficient transformer inference with only a 4% per-layer overhead compared to a fully AIMC implementation.

Artificial intelligence (AI) research today is largely driven by ever-larger neural network models trained on graphics processing units (GPUs). This paradigm has yielded remarkable progress, but it also risks entrenching a hardware lottery in which algorithmic choices succeed primarily because they align with current hardware, rather than because they are inherently superior. In particular, the dominance of transformer architectures running on GPU clusters has led to an arms race of scaling up models, resulting in exorbitant computational costs and energy usage. At the same time, today's AI models often remain unreliable in the sense that they cannot properly quantify uncertainty in their decisions-for example, large language models (LLMs) tend to produce incorrect outputs with high confidence. This paper argues that achieving more efficient and reliable AI will require embracing a set of principles that are well aligned with the goals of neuromorphic engineering, which are in turn inspired by how the brain processes information. Specifically, we outline six key neuromorphic principles, spanning algorithms, architectures and hardware, that can inform the design of future AI systems: (i) the use of stateful, recurrent models; (ii) extreme dynamic sparsity, possibly down to spike-based processing; (iii) backpropagation-free on-device learning and fine-tuning; (iv) probabilistic decision-making; (v) in-memory computing (IMC); and (vi) hardware-software co-design via stochastic computing. We discuss each of these principles in turn, surveying relevant prior work and pointing to directions for research. This article is part of the discussion meeting issue 'Bits, neurons and qubits for sustainable AI'.

Autoregressive (AR) large language models (LLMs) are inherently inefficient at inference time because each generated token requires accessing the full set of model parameters, leading to low operational intensity and high energy consumption. Masked diffusion language models (MDLMs) partially address this limitation for memory-bound settings by allowing multiple tokens to be generated per parameter access. In order to further enhance inference efficiency on modern platforms with extensive in-chip memory, this work proposes neuromorphic MDLMs (N-MDLMs), which integrate block diffusion with spike-based neuromorphic computation to jointly improve throughput and energy efficiency. While block diffusion increases token throughput by producing multiple tokens per parameter access, spike-induced sparsity reduces effective parameter traffic and computations by skipping inactive channels. To analyze the synergistic effect of sparsity and diffusion, we develop a token-level roofline-inspired model that captures the combined impact of block-parallel generation and spike sparsity on decoding efficiency. Experimental results on translation tasks show that, thanks to spike-induced sparsity, N-MDLMs achieve substantial improvements in energy efficiency and throughput even in compute-bound platforms for which MDLMs would fail to improve over AR-LLMs.

Neuromorphic computing offers an energy-efficient alternative to conventional deep learning accelerators, particularly for real-time processing of time-series data. However, many edge applications, such as wireless sensing and audio recognition, generate streaming signals with rich spectral features that are not effectively captured by conventional leaky integrate-and-fire (LIF) spiking neurons. This paper investigates a wireless split computing architecture that employs resonate-and-fire (RF) neurons with oscillatory dynamics to process time-domain signals directly, eliminating the need for costly spectral pre-processing. By resonating at tunable frequencies, RF neurons extract time-localized spectral features while maintaining low spiking activity. This temporal sparsity translates into significant savings in both computation and transmission energy. Assuming an OFDM-based analog wireless interface for spike transmission, we present a complete system design and evaluate its performance on audio classification and modulation classification tasks. Experimental results show that the proposed RF-SNN architecture achieves comparable accuracy to conventional LIF-SNNs and ANNs, while substantially reducing spike rates and total energy consumption during inference and communication.

Advances in emerging non‐volatile memories demand electrode materials that are complementary‐metal‐oxide‐semiconductor (CMOS) compatible and form atomically smooth, chemically well‐defined interfaces while enabling controlled interfacial oxygen exchange with switching layers. However, few materials simultaneously satisfy these requirements. Here, we demonstrate back‐end‐of‐line (BEOL) compatible, epitaxial WO 3 thin films sputter‐deposited at 400 °C as viable binary‐oxide bottom electrodes. To benchmark structural quality, WO 3 deposited at 500 and 700 °C was used as references, confirming that high‐quality epitaxial growth with smooth interfaces and low defect density can be achieved at BEOL‐compatible conditions. By employing chemically similar electrode and switching materials to minimise interfacial mismatch and promote stable oxygen‐vacancy (V o ) exchange, memristors are fabricated using Hf‐doped WO 3 (WHO) switching layers. These devices show electroforming‐ and current‐compliance‐free interfacial switching, operating voltages ≤±4 V, high resistance uniformity, memory‐switching ratios >130 and endurance >5 × 10 3 cycles. They further demonstrate multiple stable conductance states and linear, symmetric analogue potentiation and depression modulation. The analogue behaviour originates from combined trap‐assisted electronic conduction and field‐driven V o redistribution across an abrupt WHO/WO 3 interface. This work establishes low‐temperature‐grown epitaxial WO 3 as a reliable platform for integrating oxide electrodes into non‐volatile memory and neuromorphic electronics.

On-device fine-tuning is a critical capability for edge AI systems, which must support adaptation to different agentic tasks under stringent memory constraints. Conventional backpropagation (BP)-based training requires storing layer activations and optimizer states, a demand that can be only partially alleviated through checkpointing. In edge deployments in which the model weights must reside entirely in device memory, this overhead severely limits the maximum model size that can be deployed. Memory-efficient zeroth-order optimization (MeZO) alleviates this bottleneck by estimating gradients using forward evaluations alone, eliminating the need for storing intermediate activations or optimizer states. This enables significantly larger models to fit within on-chip memory, albeit at the cost of potentially longer fine-tuning wall-clock time. This paper first provides a theoretical estimate of the relative model sizes that can be accommodated under BP and MeZO training. We then numerically validate the analysis, demonstrating that MeZO exhibits accuracy advantages under on-device memory constraints, provided sufficient wall-clock time is available for fine-tuning.

The integration of neuromorphic computing and transformers through spiking neural networks (SNNs) offers a promising path to energy-efficient sequence modeling, with the potential to overcome the energy-intensive nature of the artificial neural network (ANN)-based transformers. However, the algorithmic efficiency of SNN-based transformers cannot be fully exploited on GPUs due to architectural incompatibility. This article introduces Xpikeformer, a hybrid analog-digital hardware architecture designed to accelerate SNN-based transformer models. The architecture integrates analog in-memory computing (AIMC) for feedforward and fully connected layers, and a stochastic spiking attention (SSA) engine for efficient attention mechanisms. We detail the design, implementation, and evaluation of Xpikeformer, demonstrating significant improvements in energy consumption and computational efficiency. Through image classification tasks and wireless communication symbol detection tasks, we show that Xpikeformer can achieve inference accuracy comparable to the GPU implementation of ANN-based transformers. Evaluations reveal that Xpikeformer achieves a $13\times $ reduction in energy consumption at approximately the same throughput as the state-of-the-art (SOTA) digital accelerator for ANN-based transformers. In addition, Xpikeformer achieves up to $1.9\times $ energy reduction compared to the optimal digital ASIC projection of SOTA SNN-based transformers.

This paper introduces a novel in-context learning (ICL) framework, inspired by large language models (LLMs), for soft-input soft-output channel equalization in coded multiple-input multiple-output (MIMO) systems. The proposed approach learns to infer posterior symbol distributions directly from a prompt of pilot signals and decoder feedback. A key innovation is the use of prompt augmentation to incorporate extrinsic information from the decoder output as additional context, enabling the ICL model to refine its symbol estimates iteratively across turbo decoding iterations. Two model variants, based on Transformer and state-space architectures, are developed and evaluated. Extensive simulations demonstrate that, when traditional linear assumptions break down, e.g., in the presence of low-resolution quantization, ICL equalizers consistently outperform conventional model-based baselines, even when the latter are provided with perfect channel state information. Results also highlight the advantage of Transformer-based models under limited training diversity, as well as the efficiency of state-space models in resource-constrained scenarios.

Neuromorphic computing, inspired by biological processes, leverages spiking neural networks (SNNs) for efficient inference with sequential data. Recent advances demonstrate that embedding bits within each spike exchanged between neurons can boost accuracy. In a split computing architecture with neuromorphic semantic communication, in which the SNN spans two devices connected wirelessly, the first device must transmit spike information from its output neurons to the second device. This setup requires balancing the benefits of multilevel spikes with the challenges of wirelessly transmitting additional bits between devices. This paper explores a neuromorphic wireless semantic communication architecture with multi-level SNNs, introducing a digital modulation scheme optimized for an orthogonal frequency-division multiplexing (OFDM) radio interface. Simulations reveal performance gains from multi-level SNN models and identify the optimal payload size based on transmitter-receiver connection quality.

Bayesian Neural Networks (BNNs) generate an ensemble of possible models by treating model weights as random variables. This enables them to provide superior estimates of decision uncertainty. However, implementing Bayesian inference in hardware is resource-intensive, as it requires noise sources to generate the desired model weights. In this work, we introduce Bayes2IMC, an in-memory computing (IMC) architecture designed for binary BNNs that leverages the stochasticity inherent to nanoscale devices. Our novel design, based on Phase-Change Memory (PCM) crossbar arrays eliminates the necessity for Analog-to-Digital Converter (ADC) within the array, significantly improving power and area efficiency. Hardware-software co-optimized corrections are introduced to reduce device-induced accuracy variations across deployments on hardware, as well as to mitigate the effect of conductance drift of PCM devices. We validate the effectiveness of our approach on the CIFAR-10 dataset with a VGGBinaryConnect model containing 14 million parameters, achieving accuracy metrics comparable to ideal software implementations. We also present a complete core architecture, and compare its projected power, performance, and area efficiency against an equivalent SRAM baseline, showing a 3.8 to 9.6x improvement in total efficiency (in GOPS/W/mm(2)) and a 2.2 to 5.6x improvement in power efficiency (in GOPS/W). In addition, the projected hardware performance of Bayes2IMC surpasses most memristive BNN architectures reported in the literature, achieving up to 20% higher power efficiency compared to the state-of-the-art.

We investigate the effects of lateral electrode shifting (skewing) in vertical metal-insulator-metal (MIM) resistive switching (RS) devices made of thin film oxides using a multiscale simulation platform. Incorporating relevant defect dynamics and electronic and thermal transport models, we compare the forming, set/reset, and voltage pulse-based conductance programming of skewed electrode devices and standard vertical memristor. Our simulations indicate that lateral electrode shift enables filament confinement during forming, reset and set processes, and influences RS behaviour due to prominent edge electric fields and introduces multi-level resistance states, making them promising for neuromorphic device applications.

Sequence models have demonstrated the ability to perform tasks like channel equalization and symbol detection by automatically adapting to current channel conditions. This is done without requiring any explicit optimization and by leveraging not only short pilot sequences but also contextual information such as long-term channel statistics. The operating principle underlying automatic adaptation is in-context learning (ICL), an emerging property of sequence models. Prior art adopted transformer-based sequence models, which, however, have a computational complexity scaling quadratically with the context length due to batch processing. Recently, state-space models (SSMs) have emerged as a more efficient alternative, affording a linear inference complexity in the context size. This work explores the potential of SSMs for ICL-based equalization in cell-free massive MIMO systems. Results show that selective SSMs achieve comparable performance to transformer-based models while requiring approximately eight times fewer parameters and five times fewer floating-point operations.

Inspired by biological processes, neuromorphic computing leverages spiking neural networks (SNNs) to perform inference tasks, offering significant efficiency gains for workloads involving sequential data. Recent advances in hardware and software have shown that embedding a small payload within each spike exchanged between spiking neurons can enhance inference accuracy without increasing energy consumption. To scale neuromorphic computing to larger workloads, split computing — where an SNN is partitioned across two devices—is a promising solution. In such architectures, the device hosting the initial layers must transmit information about the spikes generated by its output neurons to the second device. This establishes a trade-off between the benefits of multi-level spikes, which carry additional payload information, and the communication resources required for transmitting extra bits between devices. This paper presents the first comprehensive study of a neuromorphic wireless split computing architecture that employs multi-level SNNs. We propose digital and analog modulation schemes for an orthogonal frequency division multiplexing (OFDM) radio interface to enable efficient communication. Simulation and experimental results using software-defined radios reveal performance improvements achieved by multi-level SNN models and provide insights into the optimal payload size as a function of the connection quality between the transmitter and receiver.

Atomic receivers based on Rydberg vapor cells as sensors of electromagnetic fields offer a promising alternative to conventional radio frequency front-ends. In multi-antenna configurations, the magnitude-only, phase-insensitive measurements produced by atomic receivers pose challenges for traditional detection methods. Existing solutions rely on two-step iterative optimization processes, which suffer from cascaded channel estimation errors and high computational complexity. We propose a channel state information (CSI)-free symbol detection method based on in-context learning (ICL), which directly maps pilot-response pairs to data symbol predictions without explicit channel estimation. Simulation results show that ICL achieves competitive accuracy with higher computational efficiency compared to existing solutions.