Random defectivity reduction is an important prerequisite to achieving mature production yields. The typical technology roadmap includes a product yield / defect density reduction curve over the technology lifetime. Translating the defect density reduction curve into specific monthly targets for each individual module or for each single tool, has proven to be an extremely challenging task. This paper summarizes a proposed method to translate overall technology or product yield targets into corresponding defect density targets allocated to each tool. Achieving this task requires extensive characterization and modeling. This method was eventually used at a fab running 130nm 6 metal layer copper process.

Typically equipment PM optimization and strategy is determined using a mix of various sources and inline inspection. In this work, the need for a more yield aware optimization strategy is recognized and recommendations made to implement this.

An effective yield ramp methodology is demonstrated using Fail Signature Detection Algorithm (FSDA). Wafers with similar yield spatial patterns are grouped together to find stronger correlations to equipment data. Many signals that would have been missed otherwise were found leading to significant yield improvement.

This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test chips that we call Characterization Vehicle test chips and IC product layout and a set of proprietary yield models - computes detailed contributions of different yield models, of geometrical chip regions and of parts of the chip circuitry to the overall chip yield. The organization of the computed output allows easy comparison of predicted yields to inspection and electrical test measurements, where the electrical tests can include failure bit maps for memories and scan tests results for logic circuits. After we review the concept of the Yield Impact Matrix, we define a more general Micro-Event paradigm and introduce the Extended YIMP. We discuss its application to yield loss root-cause analysis, review related work and present example applications of the overall system built around this concepts.

The oxide polishing characteristics of fine-linewidth features typically encountered inrealistic chip layouts have been examined using electrical test structures. Even at these smalldimensions, we find that global pattern density plays a major role in determining the final polishedoxide thickness. In addition, differences in the initial dielectric deposition profile forsmall features produces an apparent pitch effect which must also be taken into account. Basedon experimental results,...

CMP planarization of oxide results in excellent long-range uniformity compared to other planariza-tion techniques but remains hampered by systematic pattern sensiti vities. In the recent literature, se veral semi-empirical or physically-based models have been proposed to explain ILD thickness pattern sensitivities in CMP, but all of these models either fail to predict key empirical results, are not described fully, or do not present tractable closed form models. In this paper, we de velop and derive a closed form model for ILD thickness variation and verify this model on datasets obtained o ver different polishing tools, consumable sets, and process conditions, and as a function of polishing time.

A methodology has been developed as part of a statistical metrology framework (1) to assess the relative range and distribution of intra-die, or die-level, polysilicon critical dimension variation as opposed to wafer-level, or inter-die, poly-CD variation; (2) to identify the key layout factors involved in poly-CD intra-die variation; and (3) to develop first-order semi-empirical models for poly-CD variation. A new approach utilizing multivariate analysis of variance methods is described to model the die- and wafer- level variation components. We show that pattern dependent variation is approximately twice as large as wafer-level variation. In addition, we find that spatial position plays a strong role: the first-order pattern dependent variation model (or die 'signature') shows a strong dependence on spatial position across the wafer, and individual components of the model demonstrate different spatial position sensitivities.