ALD coatings have been developed to protect process equipment against aggressive process conditions, specifically fluoride plasma. Here alumina and yttria based ALD coatings were deposited in a large-batch ALD reactor on silicon samples and mock-up showerheads. High conformality in 1:20 aspect ratio features was demonstrated. Plasma etch testing of the film revealed high resistance against the etch process for all the films in the Al2O3-Y2O3 system. Y2O3 mixing into the Al2O3 film was shown to rapidly increase the etch resistance of the film with diminishing effect as pure yttria was approached. Etch damage on the film was uniform showing no preference on grain boundaries or other features.
As semiconductor devices become more complex, the amount of sensor data from manufacturing equipment also increases, resulting in an increase in the number of abnormal behavior cases not confirmed by existing methods. To address this, we use the weighted gene co-expression network analysis (WGCNA) method from the bioinformatics field for monitoring equipment health 1) constructing sensor co-expression networks, 2) identifying modules and their significance, and 3) detecting abnormal sensors using a graphical approach. This method led to a 0.3% increase in yield rate by improving the similarity between sensors and modifying the manufacturing process conditions.
Industrial semiconductor electrodeposition plating cells require recirculation of process chemical with consistent flow and minimal contaminants to prevent defects from developing during film deposition. This manuscript investigates how recirculation nozzle quality and poor nozzle machining can affect bath chemical uniformity. Computational fluid dynamics simulations are utilized to visualize bath chemical velocities based on variable nozzle conditions in four case studies. Results show that strict quality control of inlet nozzles, in conjunction with proper mounting angles, induce laminar bath flow. Greater fluid uniformity and laminar flow then translate to a reduction of in-line defects and increased wafer yield.
The wafer fabrication process in semiconductor manufacturing involves thousands of sequential steps from different process modules, such as Chemical Mechanical Planarization (CMP), Chemical Vapor Deposition (CVD), Wet/Dry Etching, etc. The high complexity of the processes entails the risk of a process failure and leads to a long manufacturing cycle time and higher greenhouse gas emissions (GHG) before the wafers eventually reach the probe module for electrical tests. This is particularly evident as 3D NAND devices have been introduced into the industry as the layers are stacked vertically and more process steps are involved in the flow compared to 2D NAND. Therefore, one of the main approaches to process improvement is process simplification by restructuring the process flow to allow for less complex processes or even the elimination of steps without compromising yield and quality. In this way, wafer fabrication and the manufacturing process can be made more efficient and environmentally friendly, which not only shortens the manufacturing cycle time but also reduces the total cost per wafer (CPW) or even eliminates the capital expenses required for tool purchase in high-volume manufacturing facilities. This paper elaborates on various process evaluation methodologies and techniques by understanding the root cause of defects that motivated CMP buff insertion and defect improvement methods through cleaner chemical vapor deposition processes, optimized wet cleaning or scrubbing, or improved CMP cleaning. Some examples of such process simplification work on replacement gate (RG) NAND are discussed in this paper, such as de-ionized water (DIW) Buff CMP elimination (by upstream step Oxidation Clean optimization), Ceria based Slurry Buff CMP elimination (by improving upstream deposition cleanliness improvement), and CMP buff step with new slurry and consumable configuration for lower cost and reduction of greenhouse gas emissions.
In a world of chip shortages and constrained supply, unplanned manufacturing downtime is extremely costly. Avoiding unplanned equipment downtime through predictive maintenance results in increased yield, increased throughput, and reduced costs. An advanced statistical method for the evaluation of time series sensor data is herein proposed for the purpose of predicting equipment failures in Chemical Vapor Deposition (CVD) systems. Through the simultaneous evaluation of all available sensor data, the algorithm develops an expected model of the total process' behavior. Deviation from expected behavior may be interpreted as pointing to elevated risk of equipment failure, or of a process upset that may result in product that falls outside of manufacturers’ specifications, leading to costly containment measures, customer returns, and other costs.Examples from recent Industrial Experiments in Wafer Epitaxy processes are shared to demonstrate the efficacy of the method.
The wafer fabrication process in semiconductor manufacturing involves thousands of sequential steps from different process modules, such as Chemical Mechanical Planarization (CMP), Chemical Vapor Deposition (CVD), Wet/Dry Etching, etc. The high complexity of the processes entails the risk of a process failure and leads to a long manufacturing cycle time and higher greenhouse gas emissions (GHG) before the wafers eventually reach the probe module for electrical tests. This is particularly evident as 3D NAND devices have been introduced into the industry as the layers are stacked vertically and more process steps are involved in the flow compared to 2D NAND. Therefore, one of the main approaches to process improvement is process simplification by restructuring the process flow to allow for less complex processes or even the elimination of steps without compromising yield and quality. In this way, wafer fabrication and the manufacturing process can be made more efficient and environmentally friendly, which not only shortens the manufacturing cycle time but also reduces the total cost per wafer (CPW) or even eliminates the capital expenses required for tool purchase in high-volume manufacturing facilities. This paper elaborates on various process evaluation methodologies and techniques by understanding the root cause of defects that motivated CMP buff insertion and defect improvement methods through cleaner chemical vapor deposition processes, optimized wet cleaning or scrubbing, or improved CMP cleaning. Some examples of such process simplification work on replacement gate (RG) NAND are discussed in this paper, such as de-ionized water (DIW) Buff CMP elimination (by upstream step Oxidation Clean optimization), Ceria based Slurry Buff CMP elimination (by improving upstream deposition cleanliness improvement), and CMP buff step with new slurry and consumable configuration for lower cost and reduction of greenhouse gas emissions.
This paper discusses ways to reduce micro masking due to Copper (Cu) precipitation during reactive ion etching (RIE) to form thick top metal bond pads or inductors. Adding Argon (Ar) and Nitrogen (N2) in the over etch step during metal etch can significantly reduce micro-masking caused by Cu precipitation. The introduction of Ar and N2 can have several effects on the RIE process, such as improving the ionizing effect during Al/TiN barrier etch by altering the ion energy to effectively remove the Cu precipitation at the grain boundaries of Al and TiN interfaces
Advanced technology nodes require minimal defect density at every processing step. Wafer backside uniformity has become increasingly critical in modern high volume semiconductor manufacturing. Improvement in wafer backside cleans can benefit yield, defect reduction, and prevent expensive tool aborts. Backside defectivity not only poses a threat to high volume production but also increases scrap risk further downstream. In this paper, we present an effective backside wet cleans method in a single wafer clean toolset to remove Aluminum backside defects.
In this paper, we are proposing techniques to maximize efficiency of inspection tools with the help of machine learning algorithm. The proposed techniques optimized the selection of inspection locations to measure as many different patterns as possible. It can cover more than 99% of patterns on wafer with a very limited measurement budget ~ 100 measurement locations. This can be helpful in many applications such as model calibration, Hot spot detection, measure patterns fidelity on wafer and much more.
In this paper, we introduce a novel single piece upper electrode design to improve on wafer defects by reducing particle generation commonly observed in the OEM (Original Equipment Manufacturing) 2-layer design (Silicon (Si) on graphite (Gr)) Upper Electrode (UE). We are introducing a Single Piece Silicon Upper Electrode (SPUE) to replace the original two pieces (Silicon and Graphite) design. In this configuration, the graphite portion is replaced entirely with a single silicon layer and the helix hole bushing replaced with Torlon material. This eliminated the particle generation mechanisms as we will explain below. This is important because it facilitated improvement in Mean Time Before Clean (MTBC) by 42%, particle count was reduced by approximately 50% and sort yield improved by about 1%. That translates to a significant improvement in cost effectiveness of approximately 50%.
This paper will present a study about reducing on-product overlay (OPO) by optimizing imaging-based overlay (IBO) measurements utilizing newly developed extended wavelengths and optimal optical focus technologies on previous and current layers simultaneously in an advanced memory device process. Trends in memory device process variation using thicker/higher layer stacks along with more opaque process layers make this study especially crucial and topical to address these challenges.
In this paper, a Random Forest based run-to-run controller is developed to meet the challenges of a high-mix production. The model that relates the optimal recipe parameter with various industrial features is trained off-line from historical data. The predicted optimal recipe parameter is used on-line to tune the process condition. Numerical experiments conducted on a Chemical Mechanical Planarization process are presented to illustrate the performance of the controller. Compared with the system in production, the proposed approach demonstrates higher flexibility and efficiency.
Herein we present a novel method to improve the post-bonding alignment accuracy of substrates assembled via adhesive bonding with Benzocyclobutene (BCB). The method relies on hard BCB anchors to block misalignment. As a result, the alignment accuracy has been improved by an order of magnitude for a wide range of bonding BCB thicknesses (2-16 µm) without influencing the continuity of this adhesive layer.
Standard machine learning approaches rely on having access to all of the data relevant to a problem, but this does not map well to real-world situations comprising different entities that each have access to a subset of the information, but who do not wish to make all of their data available to each other due to commercial, legal or regulatory issues. Such cases can occur in fabs. Using data from the MADEin4 project, we show how a privacy-preserving augmented machine learning (PAML) approach can be applied to building virtual metrology models by combining data from two collaborating entities that have access to different aspects of the relevant data, and who wish to build the virtual metrology model whilst retaining control of their own data. The results show that the privacy-preserving PAML model nearly matches the performance of a model built from the pooled data, and significantly outperforms the models built using only the data available to individual entities.
High Reliability is critical for automotive chips. Currently, reliability verification has a long turnaround time (TAT), and is possible only during fab-out (VRAMP – Voltage Ramp to breakdown) or package (HTOL -High Temperature Operating Life) level [1]. This paper proposes a machine-learning (ML) based solution to predict reliability earlier during the middle of wafer processing. The solution includes first performing Fab-data augmentation (FDA) to augment the partially available measured fab data and is followed by building an ML model to identify and rank the critical processes that impact reliability. Finally, the model is used to predict the reliability of wafers to help screen them before proceeding through the rest of the expensive Fab process steps.
Fluorocarbon (CF x ) and its hydrogenated forms (CH x F y ) play important roles in fabricating high aspect ratio pattern in etching process. However, their chemical and thermal stability hinder removal of remaining residue. In this paper, we studied efficient removing of CF x residue by adopting N 2 post etch treatment. Typically in our platform, reacting with subsequent hydrofluoric acid (HF) cleaning, the remaining CF x residue possibly forms a sub-micro size particle, which drops manufacturing yield. By changing post plasma treatment gas from Ar to N 2 , F anion on the wafer surface was reduced by 79% (HPIC) and 44% within sub-layer (tof-SIMS), thereby CF x particle formation was completely suppressed. Controlling post etch treatment time and partial pressure of N 2 gas also revealed that chemical reaction between CF x residue and N* radical is the major removing factor, whereas plasma washing from ion bombardment is subsidiary. Increasing Cl 2 gas concentration in the main etching process also exhibited CF x removing effect, however, the particle formation was not fully reduced. In addition, we could demonstrate that controlling humidity in etching machine also affects subsequent wet cleaning efficiency of CF x residue.
Three dimensional Not-And (3D NAND) flash memory devices are scaling in the vertical direction to more than 200 oxide/sacrificial wordline nitride layers to further increase storage capacity and enhance energy efficiency. The accurate measurement of the thicknesses of these layers is critical to controlling stress-induced wafer warping and pattern distortion. While traditional optical metrology in the UV-vis-NIR range offers a non-destructive inline solution for high volume manufacturing, we demonstrate in this paper, that mid-IR metrology has advantages in de-correlating oxide and nitride thicknesses owing to their unique absorption signatures. Furthermore, because of the depths sensitivity of oxide and nitride absorptions, the simulated measurement results show the ability to differentiate thickness variations in the vertical zones. Good blind test results were obtained with a machine learning model trained on pseudo-references and pseudo spectra with added skew.
The Q-time limit is one of the factors influencing the productivity and yield of the semiconductor device in manufacturing process. In general, most dry etching processes leave gaseous by-products on the wafer, and Q-time defects occur when the following step is delayed. Therefore, at the development stage of a dry etching scheme, it is important to consider proper post-treatment for eliminating residual gas. O 2 plasma ashing and DSP (Diluted Sulfuric Peroxide) stripping are typical post-treatment methods for dry etching process. However, some mask materials for dry etching may be damaged by such post-treatments, so the reactivity of mask films, the treatment conditions, and the chemical properties of residual gas must be considered. This paper discusses the effective removal of ionic Q-time defects and the determination of the appropriate Q-time limit margin for dry etching process employing mask films that are susceptible to post-treatment conditions.
Periphery CMOS device control gate polysilicon etch is one of the key steps in NOR memory processing that has significant impact on device leakage current. In this paper, we discuss a method to reduce polysilicon etch aggressiveness and improve polysilicon etch rate cross-wafer uniformity. With a design of experiment (DOE) model by using electrostatic chuck (ESC) temperature and O 2 /inert gas flow in a plasma etch process, we predict inline responses and device electrical performance. A new combination of these two parameters shows a 3%-line yield improvement due to device leakage current reduction by preventing over-etching and etch punch-through damaging device gate structure.
This paper proposes a novel highly accurate virtual metrology (VM) method based on adaptive online time-series learning. The method comprises a novel time-series prediction algorithm robust against data drifts and shifts observed in semi-conductor manufacturing. The prediction algorithm incorporates time-aware data normalization and adaptive online learning. The time-aware normalizer transforms the data to suppress the effect of drifts. The adaptive online learner captures the time-varying relationship between response and inputs caused by shifts. On both simulated and real process data our approach outperforms conventional VM approaches. When applied to advanced process control (APC) on high-volume production lines at a major semiconductor manufacturer, our VM method substantially reduced variability of process outcomes.
