Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.

Correlation across applications and imaging platforms is essential and brings increased insurance for fault isolation in advance of destructive imaging. This paper demonstrates an approach for a detailed advanced packaging defect isolation and analysis workflow. To determine the effectiveness of the proposed workflow, a 28nm flip-chip was used as a test vehicle. By using this workflow, the yield in determining the fault location has increased from 60% to over 85%. To further improve the result, a surface charging mitigation scheme was used and the resulting measured correlative offset between the two systems was found to be less than 10um. This creates novel opportunities in reducing the size of the cross-section and increasing the overall throughput to find the defect, with high confidence. This workflow creates unique abilities in fault localization and analysis as it can detect both opens and shorts between the different techniques that are employed.

Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary waveform stimulation showed excellent agreement. Phase and amplitudes values extracted by classical LIT analysis and by Fourier analysis of the time resolved temperature response also coincided, as expected from the underlying system theory. In addition to a conceptual test vehicle represented by a point-shaped thermal source, two semiconductor packages with actual defects were studied and the obtained results are presented herein. The benefit of multi-parametric imaging for identification of a defect’s lateral position in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific stimulation signals. In both cases result verification was performed employing X-ray, scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) as complementary techniques.

This paper describes a 2X improvement in phase data acquisition for Lock-in Thermography (LIT). Phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. To overcome these difficulties, new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, are employed to validate improvements to data repeatability and accuracy as well as faster time to results on different advanced packaging devices such as flip chips and stack dies. Overall, our results showed a 2X faster time to more accurate and repeatable data for X, Y, and Z depth localization.

Abstract Lock-in thermography (LIT) phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. This paper describes how the use of new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, can result in improvements to data repeatability and accuracy as well as faster time to results. The new software is applied to generate the empirical phase shift versus applied lock-in frequency plot using 2.5D IC devices with known defect location. Subsequently, experimental phase shift data from reject 2.5D IC devices with unknown defect locations are obtained and compared against the empirical phase shift plot. The defect Z-depth of these devices are determined by comparing where the experimental phase shift data points lies with respect to empirical phase shift plot and validated with physical failure analysis (PFA).

In this study we demonstrate the use of phase shift of lock-in thermography (LIT) a powerful technique in characterizing the Z profile of 2.5D packages. It is interesting to have a good understanding of how a given package structure correlates with LIT phase shift. We create a short defect to validate the experimental phase model and the approach would be useful in applying to other type of 2.5D lCs.

This paper describes the use of Lock-In Thermography (LIT) technique to determine the defect Z-depth in flip chip. An empirical phase shift versus applied lock-in frequency plot for Flip-chip is first created by using samples with known defect Z-depth. The actual experimental phase shift data from reject samples with unknown defect locations are then measured and compared against the empirical phase shift plot. The defect Z-depth of these samples are determined by comparing where the experimental phase shift data points lies with respect to empirical phase shift plot and validated with Physical Failure Analysis (PFA).