In this paper, two scenarios are described to illustrate the use of voltage sensing as an aid for successful fault isolation. In the first scenario, voltage sensing with a 4-point Kelvin probe was utilized for effective fault isolation on high current consumption and low impedance devices. This was required to overcome the loading effects from probe contact resistance and ensured the device was sufficiently biased to trigger the failure. In the second scenario, an alternative TIVA analysis approach was employed on a power management IC by sensing the laser induced voltage alteration on the IC's failing Output Voltage pin instead of generically across the power domains for effective fault isolation.
A simple method for the in-situ examination of device turn-on in an Insulated Gate Bipolar Transistor (IGBT) is presented. A Ga + Focused Ion Beam (FIB) was used to mill away a wedge-shaped section from the material so as to leave the exposed devices operable by the surface gate and emitter contact pads. Through this window, a series of nanoprobing-based measurements were undertaken. Sensitive, Electron Beam Induced Current (EBIC) measurements strongly delineated both of the p/n junctions in the exposed surface, both those between the N+ emitter and the P-well or body, and between this P-body and N-drift region. Next, the gate voltages were varied and a series of EBIC images were taken of the body/drift depletion zone. Quantitative plots of the same gave an indication of when the insulated gate portion of the device turned on. Finally, a follow-up experiment showed the effect of applied bias on Active Voltage Contrast (AVC) of the junction. The results point to a method for examination of junctions and their behavior under gate bias with very little sample preparation. The results also ease some concerns about the use of GaFIB in sample prep for junction examination in failure analysis, given the detailed work that was possible.
Driven by the growing demands in artificial intelligence, health detection, and human-machine interaction, flexible pressure sensors, an indispensable branch of wearable electronics, have attracted attention for their wide range of applications. The flexible pressure sensor with a three-dimensional (3D) porous conductive sponge as the sensitive layer, whose resistance value changes with external pressure stimulation, has become a cutting-edge device. However, there are still issues on the reliability of flexible porous pressure devices composed of soft matter under sustained large pressure loads. In this work, a flexible porous pressure device developed based on polydimethylsiloxane (PDMS)/carbon black (CB)-attached porous composite sensitive layer was fabricated. The results show that PDMS can be used as a homogeneous binder to assist CB in attaching stably to the porous framework surface, avoiding the slipping and detachment of CB under the large strain of the framework. Under continuous loadings at 1000 kPa, the PDMS/CB@PDMS device did not experience significant initial resistance drift.
Dynamic hot carrier (HC) degradation behavior of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under gate voltage pulse stress with fast transition time is systematically investigated for the first time. The dynamic HC degradation is dependent on pulse rising time but independent of pulse falling time. Extremely severe HC degeneration is observed under gate voltage pulse stress with a fast transition time smaller than 20 ns. Combined with TCAD simulations, the dynamic HC degradation mechanism is discussed. The test results would be helpful for the reliability designing of the poly-Si TFTs in high-frequency applications.
In this work, the off-state current (I off ) degradation behavior of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dynamic drain voltage stress is investigated for the first time. The I off degradation is dependent on the peak voltage, the duration of base voltage and the falling time, and independent of the duration of peak voltage and the rising time. Incorporating TCAD simulations, a degradation model based on the electric field is proposed. This work provides a new approach to understanding the degradation behavior of poly-Si TFTs operated under dynamic voltage stress.
Failure Analysis (FA) is a complex laboratory activity that requires systematic documentation of all findings and conclusions obtained during an analysis to preserve knowledge acquired by engineers in this process. Current FA information systems store this data in different formats distributed across databases, file shares, wikis, or other human-readable forms. Given a large volume of generated FA data, navigating or searching for particular information is hard since machines cannot automatically process the stored knowledge and require frequent interaction with experts. This paper investigates two applications of modern Natural Language Processing (NLP) approaches to the Named Entity Recognition (NER) task. In particular, we study the performance of two techniques, spaCy, a highly regarded Python library, and the state-of-the-art BERT Language Models (LM), pretrained on semiconductors data. Our experiments show that spaCy reached precision, recall, and F1 scores of about 23%, whereas a BERT-based model achieved a precision of 51%, recall of 49%, and an F1 score of 50% on the test corpus.
This paper presents a new method for repackaging integrated circuits (ICs) into Small Outline (SO) dimensioned printed circuit boards, to enhance the effectiveness of failure analysis and testing techniques. Compared to ceramic or plastic packaging, printed circuit boards offer a cost advantage, as well as greater design and manufacturing flexibility to meet specific dimensional requirements. The repackaged sample can be used with a commercial burn-in socket without the need for any modifications. This package can be applied for front side and back side analysis. Or with epoxy filled, both front side die and back side die opened can also been modified.
Decapsulation of packaged integrated circuits is routinely conducted in failure analysis and reliability tests. In this work, we report on decapsulation of a complex packaged semiconductor device with multi-tier palladium-coated copper bond wires. Decapsulation process by oxygen-only Microwave Induced Plasma (MIP) was optimized with the goal to avoid corrosion of aluminium bond pads due to ultrasonic cleaning. In addition, we demonstrated a faster MIP process tailored specifically for exposure of large areas. In contrast to wet etching in acid, MIP ensures artifact-free decapsulation after which the wire bonds, bond pads and die were preserved in their original state, enabling further electrical tests and fault isolation to be performed on the devices. Two case studies are shown using MIP decapsulation and following fault isolation techniques to analyze Electrical Overstress (EOS) and metal bridging failures.
Miniaturization and compact IC package are the main driver for Die Attach Film (DAF) implementation. DAF as alternative to liquid epoxy to overcome problems such as epoxy bleed, uneven bond line thickness (BLT). However, one of the challenges in DAF processing is presence of delamination/ void. This work outlines the correlation between substrate topography with DAF void and die crack. The die crack with fixed location and pattern is caused by void between Die Attach Film (DAF) and substrate. DAF-Substrate separation occurs at the lower side of uneven flatness of DAP which is a "Pivot effect" underneath the die when high packing pressure in mold process and shrinkage during cross linking of mold compound. This eventually leads to die crack. Voids formation can be reduced by optimizing die attach parameter. Based on the DOE conducted, high bond delay and high bond temperature significantly improved on the voids and die crack. These findings provide insights into improving the reliability of IC packaging and optimizing the DAF process for future applications.
Analyzing nanograins smaller than 100nm in semiconductor interconnectors and packages using conventional Electron Backscatter Diffraction (EBSD) in a Scanning Electron Microscope (SEM) can be challenging. The solution for many researchers is the new transmission EBSD (t-EBSD), also known as the transmission Kikuchi Diffraction (TKD) technique, which requires TEM lamella samples with the optimized sample thickness and optimized SEM conditions at 30kV. This work explores the use of conventional EBSD geometry to analyze ultrathin metal thin films (<100nm) produced by advanced semiconductor manufacturing. The new method combines a new indexing method of pattern matching with the conventional EBSD technique, which enables the acquisition of high-quality EBSD maps from a 46 nm-thick Tungsten metallization layer on a Si wafer without the need for TEM sample preparation. The patterns were stored using a sensitive Symmetry S3 EBSD detector during the data acquisition and then reindexed using MapSweeper, the offline pattern matching software. The approach results in the improved orientation map quality with a hit rate increasing from 58.4% to 90% and the increased nanograin detection. The mean grain size was 40nm, obtained statistically from 209 grains. This simple and cost-effective approach provides an alternative to the more complex TKD technique and offers a promising solution for the analysis of nanograined metallization layers down to 50 nm in thickness.
Thermal Laser Stimulation (TLS) is a technique that is commonly used to localize defect’s location in Electrical Failure Analysis (EFA). The Seebeck Effect is utilized as a TLS method, which uses an Infrared (IR) laser beam to generate thermal variations in semiconductor devices. In motion sensor products, some failure occurs in the "edge seal" of the die, which is a ring of metal that surrounds the die and protects it from cracks, moisture, and contamination by mobile ions. The edge seal ring provides a barrier that helps to prevent these issues. In this paper, the technique discussed is used to localize resistance defects at the edge seal die of a motion sensor. This technique is used to identify the specific location of the defect while having capability to bench the device on its evaluation board.
With the growing demand of automotive chips market, our pursuit of chip yield is becoming more and more stringent. And with the further exploration on the plasma induced charging damage (PID), existing DRC are not perfect enough to track exactly the failure occurred locations. In this work, we discuss a DRC analysis methodology to localize novel PID on integrated circuit chips.
In this paper, an implementation of a computer vision (CV) algorithm with applications in failure analysis, specifically Photon Emission Microscopy (PEM), is presented. Failure analysis (FA) is a systematic optical and electrical analysis of microprocessors to root cause defects within the device [1]. PEM is one of the most used techniques in FA and the process of comparing the emission spots can be tedious and prone to human error. CV can be used for defect detection through two images comparison (from good and reject device) and defect location forecast through single image analysis. These CV techniques were successfully implemented in FA to identify a defect location with notable accuracy.
Alarm messages about radio frequency (RF) gain occur when the mobile communication base station works in the field. According to the log information, it is judged that the variable gain amplifier (VGA) of the receiving link is abnormal. The returned samples’ gain on board evaluation was much lower than the good unit, which confirms that the variable gain amplifier failed. The failed samples showed no abnormality through appearance inspection, X-ray, CSAM, and other non-destructive analyses. The emission microscope probe test found abnormal hot spots on the HBT, and focus ion beam processing was performed on the hot spot transistor; scanning electron microscopy (SEM) observed that the distance between the base metal 1(M1) and the emitter metal 2(M2) is about 0.33um, which is much smaller than the baseline(1.0um). Root cause analysis found that the M2 metal fabrication process requires two times lithography; the second lithography process mask alignment shift and without CD monitoring, resulting in a protective layer of polyimide over etched. After confirming the root cause, the foundry updated the process of M2 deposition by two times lithography to one time, and the corresponding photoresist thickness was optimized to 5.2um. After optimizing the process, the consistency of the M2 metal layer of the device is enhanced, and the yield of known good die (KGD) is increased by 0.41%.
Electrical characterization of small technology nodes is essential in failure analysis and yield improvement. The currently available nodes exhibit contacts having diameters of less than 30 nm. We investigated the influence of the contact resistance between the samples’ contacts and the probe tips placed on contacts of various technology nodes (14 nm, 10 nm, 7 nm and 5 nm) by using a 6-point measurement and applied a simple correction to the transistor curves based on these measurements. The analysis shows that contact resistances may be dominant even if all employed components are clean and that using five or six tips to characterize a transistor provides more accurate results with minimal additional effort.
In this paper, application of Inductively Coupled Plasma Mass Spectrometry (ICP-MS) in the monitoring of chemicals used in wafer fabrication as a first line of defense against wafer scrap, low yield and reliability issue was discussed. Two case studies of chemicals, 36%HCl and NH 4 OH, which were detected to be out of control limit (OOC) during regular monitoring were presented. Systematic problem-solving approach using fish bone diagram was engaged to identify the root causes of the two OOC cases. The root causes of the two OOC cases were identified to be due to the environmental condition for the HCl, and the corrosion of the valves in the central supply system for NH4OH.
Transmission electron microscope (TEM) failure analysis has been widely adopted in semiconductor manufacturing due to its ability to provide (sub)nanometer scale resolution for structure profiling, measurement, and defect characterization. However, TEM sample preparation using focused-ion beam milling can be challenging and time-consuming, which usually requires highly skilled personnel. With the advancement in software-assisted automation, TEM sample preparation has become more efficient and flexible. In this work, we evaluated the recently launched AutoTEM™ 5 software from ThermoFisher Scientific. This software provides a more user-friendly and easy-to-control workflow compared to previous versions. Other than the standard ex-situ lift-out procedure, it also enables guided automation for in-situ lift-out and inverted backside milling, making the operation more effective for users of different skill levels. Although challenges still exist in fully applying automation for all types of structures and situations, we propose a solution to maximize the benefits from automation for non-critical milling steps and/or (embedded) site-specific structures.
Huge parasitic extraction runtime is always proportional to the size of the design database and is one of the gating factors in the product design cycle. There is currently no comprehensive solution for actual selected partial parasitic extraction for what-if analysis or if the design of concern is dispersed across several domains in the System on Chip (SoC) with crucial timing specification in between. The main idea of this study is to look for a real layout size reduction solution for fast electrical change order (ECO) with full layout to schematic cross referenced to allow seamless back annotation during post-layout simulation as well as preserving the important post layout parameters. The proposed technique allowed for real database reduction prior to layout database processing and parasitic extraction, significantly reducing the size of the database and the computation time needed to complete the parasitic extraction flow. The whole database set and a trimmed version of the database are compared in the experimental results employing Silterra 0.18-m technology design. Parasitic extraction solution is using Mentor Graphics Calibre platform which consists of layout versus schematic (LVS), and parasitic extraction (PEX xRC).
In this paper, planar SiC 900 V 60 mΩ MOSFET was investigated with gate oxide reliability by gate oxide integrity and intrinsic TDDB measurement. The gate oxide showed reliable VBD of 46 V capacity and good TDDB lifetime performance. The intrinsic TDDB lifetime follows the linear E-model allows a confidential prediction of the failure rate within the lifetime less than 0.1 ppm in 20 years for +18 V and 175 °C temperature use conditions with wafers and TO-247 packages. Avalanche ruggedness was also confirmed by measurement the ruptured distribution by unclamped inductive switching (UIS) and investigated the failure location. Avalanche stability of BVDSS was confirmed and was showing reliable and robust over 900 V BVDSS.
Nowadays Very Large-Scale Integration (VLSI) technology is moving to sub-90 nm nodes, and power signal problems still become one of the most common issues. Due to the geometry shrinking and increase in circuit complexity, the failure mechanism becomes more complex. Hence, different methodologies and techniques were implemented to successfully localize the defect. In this paper, all of the discussed cases are related to the faulty internal signal. Hence, the typical methodologies and techniques are less effective to localize the defect. Thus, the combination of EOFM/EOP and micro-probing on internal signal traces enhanced fault localization of complex power leakage failure where the defect resided in the internal power management circuitry instead of causing direct power supply abnormality. Finally, physical FA revealed the cause of the failure. The defect found is usually caused by the imperfection of the metal line either open metal or shorted to another metal line.
