Graphene field effect transistors (GFETs) with top-gate and back-gate structures have been extensively used without much consideration for compatibility with graphene. A comparative study of the electrical characteristics of buried-gate GFETs and top-gate GFETs revealed that the performance of buried-gate GFETs is drastically enhanced by having a better gate controllability, achieving three times higher field effect mobility (similar to 3000 cm(2 )V(-1) s(-1)) than top-gate GFETs with on/off ratio similar to 10. Carrier scattering was also substantially improved by minimizing the fringing field effect, which is found to be the origin of high series resistance in top-gate GFETs. Moreover, we showed by electromagnetic (EM) simulation that the electric field distribution inside the transistors is more uniform at the buried-gate GFETs than the top-gate GFETs.

Persistent PMMA residue formed during a graphene transfer has been a culprit in the optimization of graphene device performance. We demonstrated a facile process to remove the PMMA residue using pulsed KrF laser annealing system at H2/Ar ambient. 10min laser annealing at 248nm could remove the PMMA residue as well as the methoxy and carboxyl function groups without causing noticeable damage to the graphene.

A graphitic capping layer was successfully formed on top of Cu interconnects at room temperature, using a pulsed KrF laser. The change in temperature of the Cu line was maintained below 380 degrees C during laser irradiation with a fluence of 312.5 mJ/cm(2). The resistance and critical current density of graphitic layer-capped Cu interconnects were improved by 2.8% and 5.2%, respectively. The lifetime of graphitic layer-capped Cu interconnects under a constant current stress was improved by 223%. (C) 2017 Elsevier Ltd. All rights reserved.

We have successfully demonstrated a graphene-ZnO:N Schottky barristor. The barrier height between graphene and ZnO:N could be modulated by a buried gate electrode in the range of 0.5-0.73 eV, and an on-off ratio of up to 107 was achieved. By using a nitrogen-doped ZnO film as a Schottky contact material, the stability problem of previously reported graphene barristors could be greatly alleviated and a facile route to build a top-down processed graphene barristor was realized with a very low heat cycle. This device will be instrumental when implementing logic functions in systems requiring high-performance logic devices fabricated with a low temperature fabrication process such as back-end integrated logic devices or flexible devices on soft substrates.

The Fermi level of graphene in contact with the metal contact is a critically important factor for graphene-based device design. Fermi level pinning like behavior at the metal on a graphene can limit the contact resistance reduction and other device operations, especially in high workfunction metal cases. We report that this problem can be substantially alleviated by the hydrogen anneal at high pressure over 20atm.

We demonstrate and explain the operation of PVDF-TrFE/graphene/ZnO:N barristor using electrostatic force microscopy (EFM) poling system. The device was successfully reconfigured using a ferroelectric polymer, PVDF-TrFE. 103 of device current modulation were achieved. And, it will be very useful for dynamically reconfigurable logic, memory and logic memory hybrid device applications.

High contact resistance and symmetrical conduction are serious challenges in practical applications of transition metal dichalcogenide (TMD) field-effect transistors (FETs). Unipolar behavior and reduced contact resistance are achieved for tungsten disulfide (WS2) FETs by using a TiO2 interfacial layer inserted between a metal layer and a WS2 layer. As a service to our authors and readers, this journal provides supporting information supplied by the authors. Such materials are peer reviewed and may be re-organized for online delivery, but are not copy-edited or typeset. Technical support issues arising from supporting information (other than missing files) should be addressed to the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Two‐dimensional transition metal dichalcogenides (TMDCs) are potential candidate materials for future thin‐film field effect transistors (FETs). However, many aspects of this device must be optimized for practical applications. In addition, low‐frequency noise that limits the design window of electronic devices, in general, must be minimized for TMD‐based FETs. In this study, the low‐frequency noise characteristics of multilayer molybdenum disulphide (MoS2) FETs were investigated in detail, with two different contact structures: titanium (Ti) metal–MoS2 channel and Ti metal–TiO2 interlayer–MoS2 channel. The results showed that the noise level of the device with a TiO2 interlayer reduced by one order of magnitude compared with the device without the TiO2 interlayer. This substantial improvement in the noise characteristics could be explained using the carrier number of fluctuation model. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)

Strong demand for power reduction in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device density and higher information density, a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addition, a standard ternary inverter working at room temperature has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technology.

There is significant interest in synthesizing large-area graphene films at low temperatures by chemical vapor deposition (CVD) for nanoelectronic and flexible device applications. However, to date, low-temperature CVD methods have suffered from lower surface coverage because micro-sized graphene flakes are produced. Here, we demonstrate a modified CVD technique for the production of large-area, continuous monolayer graphene films from benzene on Cu at 100–300 °C at ambient pressure. In this method, we extended the graphene growth step in the absence of residual oxidizing species by introducing pumping and purging cycles prior to growth. This led to continuous monolayer graphene films with full surface coverage and excellent quality, which were comparable to those achieved with high-temperature CVD; for example, the surface coverage, transmittance and carrier mobilities of the graphene grown at 300 °C were 100%, 97.6% and 1,900–2,500 cm2 V−1 s−1, respectively. In addition, the growth temperature was substantially reduced to as low as 100 °C, which is the lowest temperature reported to date for pristine graphene produced by CVD. Our modified CVD method is expected to allow the direct growth of graphene in device manufacturing processes for practical applications while keeping underlying devices intact.

High contact resistance between graphene and metal is a major huddle for high performance electronic device applications of graphene. In this work, a method to improve the contact resistance of graphene is investigated by varying the ratio of peripheral length and area of graphene pattern under a metal contact. The contact resistance decreased to 0.8 kΩ·μm from 2.1 kΩ·μm as the peripheral length increased from 312 to 792 μm. This improvement is attributed to the low resistivity of edge-contacted graphene, which is 8.1 × 105 times lower than that of top-contacted graphene.

The importance of proper graphene transfer process cannot be emphasized more because it is so closely related to the performance and stability of graphene devices. In this work, a new transfer method utilizing a voluntary bonding of a graphene film to a target substrate in vacuum is demonstrated. The problems originated from water and air molecules which prevent a robust bonding and degrade the electrical characteristics could be drastically alleviated. As a result, graphene field-effect transistors showed nearly symmetric Id–Vg characteristics with a minimal hysteresis and drastically improved device stability in air for more than a month could be obtained.

Achieving a low contact resistance for 2D materials is a critical challenge for device applications. In this work, the contact resistance of MoS 2 FETs has been drastically reduced by five times from the reference data using an optimized TiO 2 Fermi level de-pinning layer which reduced the effective Schottky barrier height to 0.1 eV. As a result, a very low contact resistance ~5.4 kΩ·μm was achieved without any doping technique.

The feasibility of a high speed ferroelectric graphene memory device using a ferroelectric polymer (PVDF–TrFE)/graphene stack has been demonstrated. The conductivity of this metal–ferroelectric–graphene (MFG) device could be modulated up to 775% with a very fast programming speed down to 10 ns. Also, programmed states were maintained up to 1000 s with endurance over 1000 cycles. In addition to demonstrating a single memory device, the array-level integration and cell write/read functionality of a 4 × 4 MFG array adopting a graphene bit line has also been confirmed to show the feasibility of MFG memory.

The benefits of multi-layer graphene (MLG) capping on Cu interconnects have been experimentally demonstrated. The resistance of MLG capped Cu wires improved by 2-7% compared to Cu wires. The breakdown current density increased by 18%, suggesting that the MLG can act as an excellent capping material for Cu interconnects, improving the reliability characteristics. With a proper process optimization, MLG capped Cu interconnects could become a promising technology for high density back end-of-line interconnects.

The role of the initial defects of graphene characterized by Raman spectroscopy is correlated with the physical mechanisms causing the hysteretic device characteristics of graphene field effect transistors (FETs). Fast charging related to the tunneling-induced charge exchange is found to be closely correlated with the initial defect density, while slow charging related to environmental influences such as the water redox reaction showed a weak correlation. It can be concluded that the intrinsic quality of graphene should be improved to minimize the hysteresis of graphene FETs even in an air-tight environment.

A new touch sensor device has been demonstrated with molybdenum disulfide (MoS2) field effect transistors stacked with a piezoelectric polymer, polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE). The performance of two device stack structures, metal/PVDF-TrFE/MoS2 (MPM) and metal/PVDF-TrFE/Al2O3/MoS2 (MPAM), were compared as a function of the thickness of PVDF-TrFE and Al2O3. The sensitivity of the touch sensor has been improved by two orders of magnitude by reducing the charge scattering and enhancing the passivation effects using a thin Al2O3 interfacial layer. Reliable switching behavior has been demonstrated up to 120 touch press cycles.

Graphene has attracted attention because of its extraordinarily high mobility. However, procedures to extract mobility from graphene metal-oxide semiconductor transistors have not been systematically established because the accuracy of mobility value is affected by many extrinsic parameters. In this work, the influence of extrinsic parameters, such as contact resistance, transient charging effect, measurement temperature, and ambient on mobility are examined in order to provide a protocol capable of accurately assessing the mobility of graphene metal-oxide-semiconductor field effect transistors. Using a well controlled test protocol, the mobility of graphene is found to be temperature independent up to 450 K.