As space missions expand in duration and complexity, ensuring the intrinsic reliability of electronics against harsh heavy-ion irradiation remains a critical challenge. Here we show that phase-composite zinc oxide topology, which embeds nanocrystals within an amorphous matrix, exhibits exceptional radiation hardness compared to conventional polycrystalline devices. Under high-linear-energy-transfer irradiation (72.3 MeV·cm2/mg[silicon]), passivated devices with rigid polycrystalline structure suffer severe electrical degradation (26.3–46.4%) in on-current, field-effect mobility, and subthreshold swing, alongside a 31-fold increase in flicker noise spectral density. Conversely, passivated devices with flexible phase-composite crystallinity maintain remarkable stability with minimal variations (2.1–8.2%) in electrical parameters, while preserving consistent carrier-number fluctuation noise behavior. Structural analyses and concurrent electrical improvements reveal that heavy-ion irradiation induces a net increase in lattice bonds within the phase-composite topology, facilitating spontaneous, radiation-assisted self-annealing. Simultaneously, distributed nanocrystals provide alternative conduction pathways that bypass local irradiation-induced defects. Ultimately, this structural synergy establishes a fundamental crystallinity-dependent design strategy for developing robust radiation-hardened electronics. As space missions expand in duration and complexity, ensuring the intrinsic reliability of electronics against harsh heavy-ion irradiation is key. Here phase-composite zinc oxide topology, which embeds nanocrystals within an amorphous matrix, exhibits enhanced radiation hardness in thin film transistors compared to conventional polycrystalline devices.

Tellurium (Te) has emerged as a promising p-type semiconductor for ultrathin electronics owing to its strong air stability, excellent hole transport, narrow bandgap, and BEOL-integration compatibility. However, when the Te thickness approaches the depletion width, traps at the contact interface strongly affect carrier injection and introduce excess low-frequency noise. Here, we systematically investigate the origin of noise in ultrathin Te field-effect transistors (FETs) through bias- and temperature-dependent 1/f noise analysis. In devices with a 5 nm Te channel, contact-origin trap-assisted tunneling dominates in the low-current regime, producing deviations from the carrier-number-fluctuation (CNF) model at 300 K. Cooling to 100 K suppresses trap activation and restores typical CNF behavior, whereas 13 nm devices maintain CNF consistency at both temperatures due to screening of the contact region. To mitigate contact-origin noise, a locally thickened (13 nm) Te layer was inserted beneath the source and drain metal contact while preserving a 5 nm active Te channel. This design restores CNF behavior at room temperature, lowers the noise level in the nA current regime by an order of magnitude, and decreases the drain-bias dependence of noise by approximately twofold. The results identify near-contact traps as the primary noise source in ultrathin Te and demonstrate contact-centric engineering as an effective strategy to decouple device scaling from noise, enabling reliable, low-noise Te electronics.

Co-integration of extremely thin n- and p-type semiconductor layers deposited in wafer-scale at low temperatures (<= 200 degrees C) opens new avenues for novel electronic devices. Here, a multi-functional ZnO-Te heterojunction device exhibiting double negative differential transconductance (D-NDT) characteristics is presented. By modulating the overlap length of n- and p-type regions, the carrier transport mechanism transitions from single NDT to D-NDT, enabling multi-state switching within a single device. Leveraging the unique double-peak transfer curve, a single-stage frequency quadrupler is demonstrated, resulting in a reduction of device count by 64%-75% compared to standard analog and digital circuit topologies. The functionality of the frequency quadrupler is verified using a system clock generator driving a 2-bit binary counter, achieving a fourfold increase in data processing throughput within a single input cycle. These results suggest that the ZnO-Te D-NDT device offers a promising pathway for realizing area-efficient and multi-functional integrated circuits for future electronics.

Tellurium (Te) is increasingly gaining attention as a scalable p-type channel material owing to its inherently high carrier mobility and ambient stability. However, in sub-5 nm Te channels, high contact resistance remains a major obstacle to achieving high-performance device operation. In this study, an estimated contact resistance of ≈1.7 kΩ·μm is obtained in 4 nm-thick Te channels by engineering the band structure in the source and drain (S/D) regions using a raised source and drain (RSD) structure. To isolate intrinsic contact behavior, electrical measurements are conducted at 77 K, in which thermally activated defect states are suppressed, and carrier injection is dominated by the metal-semiconductor interface. Transport characterization reveals a more than 17-fold increase in on-state current and a more than 50-fold reduction in contact resistance relative to Te devices without the RSD structure. This enhancement is attributed to selectively increasing the Te thickness at the S/D terminals, which tunes the bandgap by thickness-dependent modulation. The resulting RSD architecture enhances tunneling current by narrowing the barrier width─modulated by gate bias. This scalable, low-temperature approach offers broad applicability to other ultrathin channel materials.

This study investigates the impact of high-energy proton irradiation (33 and 100 MeV) on the radiation response and statistical uniformity of the breakdown field of HfxZr1−xO2 based metal–insulator–metal capacitors. While macroscopic electrical characteristics—such as polarization hysteresis, dielectric constant, and leakage current—exhibit remarkable radiation stability across various crystalline phases, a distinct improvement is observed in the statistical distribution of the breakdown field (EBD). Weibull distribution analysis reveals a consistent increase in the shape factor (β) following irradiation, indicating a "healing effect" that effectively narrows the variance of dielectric breakdown. This enhancement leads to a normalized yield improvement ranging from 3.0

The influence of crystal structure on the radiation hardness of ZnO thin-film transistors (TFTs) under heavy-ion irradiation is investigated through a comparative analysis between conventional polycrystalline ZnO (Poly-ZnO) and phase-composite $\mathbf{Z n O}(\mathbf{P h C}-\mathbf{Z n O})$. To isolate the intrinsic effects of crystallinity from surface-driven instabilities, an $\text{Al}_{2} \mathrm{O}_{3}$ passivation layer was employed to stabilize the channel interface. While Poly-ZnO TFTs suffer significant degradation in on-current, field-effect mobility, and subthreshold swing due to atomic displacement damage within polycrystalline grains, PhC-ZnO TFTs exhibit remarkable stability with negligible changes. This robustness is attributed to the unique micro-topology of PhC-ZnO-comprising nanocrystalline domains dispersed within an amorphous matrix-which acts as a structural buffer to preserve carrier transport integrity. This study provides a new design rule for engineering intrinsically radiation-hardened metal-oxide semiconductors via precise crystallinity control.

A hardware-efficient, current-mode pattern classifier is proposed using ZnO–Te heterojunction devices. The ZnO–Te heterojunction exhibits Λ-shaped anti-ambipolar characteristics, enabling gate-selective current switching. By exploiting these characteristics, a current-output XOR cell is implemented using only 3 devices, whereas a conventional CMOS XOR requires 10 transistors. This current-mode operation allows mismatch currents to be summed directly on a shared line, eliminating the need for a complex digital popcount adder tree. HSPICE simulations, incorporating heterojunction device XOR arrays and current sense amplifiers, verify 2-bit mismatch detection and 9-bit (3 × 3 pixel) classifier operations. Device-count analysis demonstrates substantial hardware reductions: from 134 to 19 devices (~85.8%) for a 2 × 2 classifier and from 1,374 to 115 devices (~91.6%) for a 6 × 6 classifier. These results highlight the potential of ZnO–Te heterojunctions for compact and energy-efficient AI hardware.

In this study, the effects of interface engineering on two types of nanoscale devices were investigated under gamma-ray and high-energy proton irradiation. The effects of gamma-ray irradiation on the electrical variations of molybdenum disulfide ($\text{MoS}_{2}$) field-effect transistors (FETs) with a buried local back-gate structure were investigated, revealing that device instability is mainly caused by interface carrier trap sites. Additionally, the radiation hardness of high-energy protons in ZnO thin-film transistors (TFTs) with a 3.5 nm thickness was investigated. $\text{An} \text{Al}_{2} \mathrm{O}_{3}$ passivation layer was introduced to significantly improve the radiation hardness of ZnO TFTs against high-energy protons of up to 100 MeV. These results suggest that irradiationinduced variability in nanoscale devices is mainly caused by interface states rather than the device itself and can be significantly minimized through interface engineering.

Self‐powered photodetectors (SPPDs) have attracted significant attention as a key component of future technologies that require ultra‐low power consumption, such as mobile edge devices. Molybdenum disulfide (MoS 2 ), a representative van der Waals semiconductor, has emerged as a promising SPPD candidate due to its superior optoelectronic properties compared to conventional bulk materials. However, forming a pn photodiode with MoS 2 is challenging due to its strong n ‐type characteristics and the presence of nonideal metal–semiconductor interfaces. Here, high‐performance MoS 2 SPPDs are reported, exhibiting a photoresponsivity exceeding 21 A W −1 , a detectivity as high as 3.7 × 10 13 Jones, and a rectification ratio over 10 7 , without requiring complex heterostructures, chemical doping, or multiple gates. To realize an ideal MoS 2 pn junction, Pt and graphite asymmetric bottom electrodes are introduced into a partial‐gate architecture, where hole injection is notably facilitated. The clearly developed ambipolar behavior of MoS 2 with Pt bottom contacts allows for the estimation of band modulation efficiency and corresponding built‐in potential, close to the MoS 2 bandgap, across the high‐quality pn junction. The self‐powered photodetection phenomenon is electrically tunable, as demonstrated through extensive electrical and optoelectrical characterization, including scanning photocurrent microscopy, combined with theoretical analysis.

Ultrathin oxide semiconductors are promising channel materials for next-generation thin-film transistors (TFTs), but their performance is severely limited by bulk and interface defects as the channel thickness approaches a few nanometers. In this study, we show that high-pressure hydrogen annealing (HPHA) effectively mitigates these limitations in 3.6 nm thick ZnO TFTs. HPHA-treated devices exhibit a nearly four-fold increase in on-current, a steeper subthreshold swing, and a negative shift in threshold voltage compared to reference groups. X-ray photoelectron spectroscopy reveals a marked reduction in oxygen vacancies and hydroxyl groups, while capacitance–voltage measurements confirm more than a three-fold decrease in interface trap density. Low-frequency noise analysis further demonstrates noise suppression and a transition in the dominant noise mechanism from carrier number fluctuation to mobility fluctuation. These results establish HPHA as a robust strategy for defect passivation in ultrathin oxide semiconductor channels and provide critical insights for their integration into future low-power, high-density electronic systems.

We studied the effects of the interface oxide layer between amorphous indium-gallium-zinc oxide (IGZO) and metallic electrodes on contact resistance (RC). The reduction of RC has become imperative as IGZO devices are scaled down to achieve higher on current. Previous studies have reported the formation of low-resistance ohmic contacts, wherein oxygen vacancies generated by reactions between IGZO and metal supply free electrons. Nonetheless, such reactions inevitably lead to the formation of a high-resistivity interface oxide and the creation of defect states. In this study, we employed alkyl-phosphonic acid self-assembled monolayers (SAMs) with precisely controlled nanometer-scale thickness to minimize RC in IGZO transistors. The optimized SAM effectively suppressed interface oxide formation between IGZO and the metal, reducing the thickness from 11 to 4.1 nm. Additionally, the SAM passivated dangling bonds on the IGZO surface, thereby facilitating electron transport with diminished trapping and detrapping phenomena. Consequently, despite the insulating properties of the SAM, the RC was markedly decreased by 77%, and the shortening of the effective channel length was reduced by 37% following thermal stress at 150 °C.

Self-powered photodetectors (SPPDs) have attracted significant attention as a key component of future technologies that require ultra-low power consumption, such as mobile edge devices. Molybdenum disulfide (MoS2), a representative van der Waals semiconductor, has emerged as a promising SPPD candidate due to its superior optoelectronic properties compared to conventional bulk materials. However, forming a pn photodiode with MoS2 is challenging due to its strong n-type characteristics and the presence of nonideal metal-semiconductor interfaces. Here, high-performance MoS2 SPPDs are reported, exhibiting a photoresponsivity exceeding 21 A W-1, a detectivity as high as 3.7 x 1013 Jones, and a rectification ratio over 107, without requiring complex heterostructures, chemical doping, or multiple gates. To realize an ideal MoS2 pn junction, Pt and graphite asymmetric bottom electrodes are introduced into a partial-gate architecture, where hole injection is notably facilitated. The clearly developed ambipolar behavior of MoS2 with Pt bottom contacts allows for the estimation of band modulation efficiency and corresponding built-in potential, close to the MoS2 bandgap, across the high-quality pn junction. The self-powered photodetection phenomenon is electrically tunable, as demonstrated through extensive electrical and optoelectrical characterization, including scanning photocurrent microscopy, combined with theoretical analysis.

Combinations of n- and p-type semiconductors (with thicknesses of a few nanometers or ultrathin) deposited at low temperatures are creating new opportunities for novel devices and circuits. We demonstrate an antiambipolar switch (AAS) device using a heterojunction comprising extremely thin ZnO and Te layers operating at a complementary metal-oxide semiconductor (CMOS)-compatible bias (similar to 1.2 V) with a high peak-to-valley ratio (similar to 104). The entire process was performed at a full wafer scale with a low thermal budget at temperatures below 150 degrees C. The device count and area of the binary-to-ternary converter designed with this device were reduced by similar to 95% and similar to 97%, respectively. In addition, we demonstrate a few examples of binary-ternary logic circuits to show that the system complexity and computing efficiency of the binary CMOS architecture can be dramatically improved by easily cointegrating the ZnO-Te AAS-based converter in the back-end-of-line structure.

Oxide-based memristor is an attractive candidate for future nonvolatile resistive random access memory (RRAM) devices. However, it suffers from insufficient reliability, owing to the randomness of the conductive filaments, hindering the practical use of the memristor for future RRAM applications. Here, we propose harnessing the twodimensional (2D) transition metal dichalcogenides (TMDs) on oxide memristor to achieve high device reliability by controlling oxygen vacancy-based filaments near the TMDs/oxide interface. By forming the Pt/WSe2/ HfxZr1-xO2 (HZO)/TiN structure, the fabricated memristor exhibits high reliability with good cyclic endurance (over 2,000 cycles), retention (104 s), and low cycle-to-cycle variability. Surface chemical analysis reveals the abundant oxygen vacancies induced by forming WSe2/HZO interface are the source of filamentary switching. By incorporating 2D materials and oxides, the practical application of memristor to future information processing devices can be boosted by the enhanced device reliability.

A novel approach to delicately control the phase of a ferroelectric has been developed using a continuous-wave laser scanning annealing (CW-LSA) process. After proper process optimization, the equivalent oxide thickness (EOT) of 3.5 & Aring; with a dielectric constant (kappa) of 68 & Aring; is achieved from HZO in a metal-ferroelectric-metal (MFM) capacitor structure. The leakage current density (J g = 4.6 x 10-5 A/cm2 at +0.8 V) was four times lower compared to the reference group treated with an optimized RTA process. The outstanding electrical characteristics of the 6 nm HZO film were attributed to the stable formation of the morphotropic phase boundary (MPB) structure, which was enabled by the directional scanning nature of the CW-LSA process.

Te is a promising p-type semiconductor, but its narrow bandgap (similar to 0.7 eV), high off-state current, electrical hysteresis, DIBL-like behavior, and difficulty in achieving enhancement-mode operation hinder practical use. We argue that many of these issues arise from misinterpreting Te Schottky barrier (SB) FETs as conventional MOSFETs and relying solely on room-temperature measurements. To address this, we propose three key strategies: (1) suppressing oxygen-related defects from Te channel, (2) engineering Schottky barriers at metal/Te interface to reduce contact resistance (RC), and (3) performing low-temperature characterization. Using these approaches, we demonstrate enhancement-mode Te FETs with negligible hysteresis and DIBL, and low RC (1.5 k Omega.mu m) and high hole mobility (54 cm(2)/V.s).

Metal-oxide thin-film semiconductors have been highlighted as next-generation space semiconductors owing to their excellent radiation hardness based on their dimensional advantages of very low thickness and insensitivity to crystal structure. However, thin-film transistors (TFTs) do not exhibit intrinsic radiation hardness owing to the chemical reactions at the interface exposed to ambient air. In this study, significantly enhanced radiation hardness of Al2O3-passivated ZnO TFTs against high-energy protons with energies of up to 100 MeV is obtained owing to the passivation layer blocking interactions with external reactants, thereby maintaining the chemical stability of the thin-film semiconductor. These results highlight the potential of passivated metal-oxide thin films for developing reliable radiation-hardened semiconductor devices that can be used in harsh space environments. In addition, the relationship between low-frequency noise and defects due to oxygen vacancies was revealed, which can be utilized to improve device reliability.

Multi-valued logic is the subject of ongoing investigation owing to its potential to reduce the complexity of logic circuits and interconnect lengths, thereby reducing system power consumption. In this work, ternary stack channel field-effect transistors (SCFETs) are used as unit devices to realize multi-valued logic. The thickness of each ZnO layer in the SCFET is modulated to obtain the device parameters to control the intermediate-state range and saturation current. Using the experimental results, ternary circuits are modeled and simulated to demonstrate that the unique characteristics of SCFETs can be utilized in designing a ternary full adder. The designed ternary full adder requires only 12 devices (approximately 29% of the binary full adder device count). The ternary serial adder has a competitive power-delay product value of approximately 7 fJ at V DD = 1 V and an effective oxide thickness of 1 nm. These results indicate that SCFET-based ternary circuits are a promising alternative for extremely low-power applications.

The complementary field‐effect transistor (CFET) structure is a highly area‐efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recrystallization, which has been limiting further development. In this paper, an alternative method is proposed to realize CFETs using p‐type tellurium (Te) (for the lower‐level channel) and n‐type zinc oxide (ZnO) (for the upper‐level channel). Te and ZnO are directly deposited on a 30 × 30 mm 2 SiO 2 /Silicon substrate, using a considerably low‐temperature fabrication process (<150 °C). The lower p‐type channel exhibits superior mobility exceeding 10 cm 2 V −1 s −1 even after the integration of the entire CFET process. The CFET inverter demonstrates a voltage gain >51 at V DD = 4 V and noise margins of 0.36 and 0.45 V at V DD = 1 V. Using the same integration process, functional NAND and NOR logic gates are successfully demonstrated in the vertically integrated CFET structure. The proposed ZnO/Te CFET can be a promising device technology, particularly for 3D and heterojunction integration requiring a low thermal budget.

In this work, a novel hydrogen process is proposed to enhance the stability of IGZO transistors without side effects such as defect generation or negative threshold voltage (V TH ) shift. Conventional hydrogen treatments on IGZO transistors, including thermal annealing and plasma, typically resulted in excess hydrogen incorporation, leading to unstable states like M─OH bonds and hydrons, which degrade electrical stability. This approach integrates a post‐annealing process step following plasma treatment, eliminating undesired hydrogen‐related states while preserving only beneficial and stable hydrogen bonds. The hydroxyl radicals formed during hydrogen plasma are converted into highly reactive oxygen radicals in an oxygen‐rich environment. These oxygen radicals subsequently passivate oxygen vacancies to form stable M─O bonds. Compared to bare devices, interface/bulk trap densities are reduced by 90% and 86%, respectively, after the hydrogen process; this is attributed to the effective removal of deep‐level oxygen defects and the formation of stable M─O bonds during the post‐annealing process. As a result, IGZO transistors treated with this hydrogen process showed a significant reduction in ∆V TH under positive gate‐bias and negative gate‐bias illumination stresses by 83% and 62%, respectively, along with high field‐effect mobility (15.14 ± 0.39 cm 2 V s −1 ), subthreshold slope (90 ± 5.9 mV dec −1 ), and I on /I off ratio (>10 7 ).