The Linear Collider Flavour Identification (LCFI) Collaboration is developing the sensors, readout electronics and mechanical support structures for the vertex detector of the International Linear Collider (ILC). High speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below the 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs), Column Parallel Readout chips (CPRs) and Column Parallel Driver chips (CPDs) have been developed. The CPCCD has to operate at a clock frequency of 50 MHz, which represents a difficult technical challenge due to the large sensor capacitance. The design and performance of the second generation CPCCD sensors, CPC2, and the new driver chip, CPD1, which meet these challenging requirements, are described.

The vertex detectors at the International Linear Collider (ILC) (there will be two of them, one for each of two general purpose detectors) will certainly be built with silicon pixel detectors, either monolithic or perhaps vertically integrated. However, beyond this general statement, there is a wide range of options supported by active R&D programmes all over the world. Pixel-based vertex detectors build on the experience at the SLAC large detector (SLD) operating at the SLAC linear collider (SLC), where a 307 Mpixel detector permitted the highest physics performance at LEP or SLC. For ILC, machine conditions demand much faster readout than at SLC, something like 20 time slices during the 1 ms bunch train. The approach of the image sensor with in-situ storage (ISIS) is unique in offering this capability while avoiding the undesirable requirement of ‘pulsed power’. First results from a prototype device that approaches the pixel size of 20 μm square, needed for physics, are reported. The dimensional challenge is met by using a 0.18 μm imaging CMOS process, instead of a conventional CCD process.

The precision measurements envisaged at the International Linear Collider (ILC) depend on excellent instrumentation and reconstruction software. The correct identification of heavy flavour jets, placing unprecedented requirements on the quality of the vertex detector, will be central for the ILC programme. This paper describes the LCFIVertex software, which provides tools for vertex finding and for identification of the flavour and charge of the leading hadron in heavy flavour jets. These tools are essential for the ongoing optimisation of the vertex detector design for linear colliders such as the ILC. The paper describes the algorithms implemented in the LCFIVertex package, as well as the scope of the code and its performance for a typical vertex detector design.

The in situ storage image sensor (ISIS) is a monolithic active pixel sensor with memory cells in each pixel. The memory cells are implemented as a CCD register. This and other features of the sensor make the ISIS an excellent device for detectors that will be used at the International linear collider (ILC), an electron-positron accelerator with a proposed centre-of-mass energy of around 500 GeV. The sensor can be made very thin while retaining a high signal-to-noise ratio. The memory cells can be read out between bunch trains at a relatively low clock speed, hence limiting power consumption. The actual signal charge is stored in potential wells and not on capacitors, minimizing the sensitivity to electromagnetic interference. This paper presents the results of the first beam test of the first ISIS prototype. The measurements made include the signal-to-noise ratio, position resolution and efficiency.

The Linear Collider Flavour Identification (LCFI) collaboration has successfully developed the first prototype of a novel particle detector, the In-situ Storage Image Sensor (ISIS). This device ideally suits the challenging requirements for the vertex detector at the future International Linear Collider (ILC), combining the charge storing capabilities of the Charge-Coupled Devices (CCD) with readout commonly used in CMOS imagers. The ISIS avoids the need for high-speed readout and offers low power operation combined with low noise, high immunity to electromagnetic interference and increased radiation hardness compared to typical CCDs. The ISIS is one of the most promising detector technologies for vertexing at the ILC. In this paper we describe the measurements on the charge-shielding properties of the p-well, which is used to protect the storage register from parasitic charge collection and is at the core of device's operation. We show that the p-well can suppress the parasitic charge collection by almost two orders of magnitude, satisfying the requirements for the application.

The In Situ Storage Image Sensor (ISIS) is a monolithic active pixel sensor with memory cells in each pixel. The memory cells are implemented as a CCD register. A test device with parameters suitable for tracking charged particles has been constructed and characterized. The characteristics of a proof-of-principle ISIS device are described and results from using the sensor as a tracking device for high energy electrons are presented.

The LCFI Collaboration is developing the sensors, readout electronics and mechanical support structures for the Vertex Detector (VXD) of the International Linear Collider (ILC). High-speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs) and Column Parallel Readout chips (CPRs) have been developed. The CPCCD has to operate at a clock frequency of 50 MHz, which represents a difficult technical challenge due to the relatively large sensor capacitance. The design and performance of planar transformers, which can be used to provide the required 20 A clock current, are described.

The LCFI Collaboration is developing the sensors, readout electronics and mechanical support structures for the vertex detector (VXD) of the International Linear Collider (ILC), as well as studying the physics performance that the VXD will achieve. Since the VXD must provide excellent spatial resolution, the sensors must have very low mass and their power consumption must be small to ensure that the sensors themselves cause as little multiple scattering as possible and that gas cooling can be used to operate them at temperatures of about −40C. High-speed readout is also needed to ensure that the occupancy due to the pair production background at the ILC is kept below the 1% level. In order to satisfy these strict requirements, Column Parallel CCDs (CPCCDs) and Column Parallel Readout chips (CPRs) have been developed. The readout chips must be able to operate synchronously with the CPCCDs and ensure fast signal processing with low noise and data compression. The design and performance of the latest version of the readout chip, the CPR2A, are described here.

Results of detailed simulations of the charge transfer inefficiency of a prototype CCD chip are reported. The effect of radiation damage in a particle detector operating at a future accelerator is studied by examining two electron trap levels, 0.17 eV and 0.44 eV below the bottom of the conduction band. Good agreement is found between simulations using the ISE-TCAD DESSIS program and an analytical model for the 0.17 eV level. Optimum operation is predicted to be at about 250K where the effects of the traps is minimal which is approximately independent of readout frequency. This work has been carried out within the Linear Collider Flavour Identification (LCFI) collaboration in the context of the International Linear Collider (ILC) project.

This document describes the progress of the Linear Collider Flavour Identification (LCFI) Collaboration since the last report to the DESY Physics Research Committee in April 2005. In the intervening period, the Collaboration has successfully operated Column Parallel Charge-Coupled Devices (CPCCDs) at 45 MHz, close to the frequency of 50 MHz needed for the inner layer of the Vertex Detector (VXD) of the International Linear Collider (ILC), and has designed and manufactured a chip capable of producing the clock signals needed to drive the CPCCD. Progress has also been made with the development of Column Parallel Readout (CPR) chips for the CPCCD, allowing thresholds to be applied to the CPCCD data and on-chip clustering and sparsification. CPR chips have been successfully bump-bonding to CPCCD sensors and used for read out. The functioning of the In-situ Storage Image Sensor (ISIS) concept has been demonstrated and a second generation ISIS design is nearing completion. The Collaboration has identified materials which allow the construction of ladders with a thickness of 0.1%X0, the target value for the ILC, and has constructed and surveyed test ladders using these materials. Sophisticated software for vertex finding, flavour identification and quark charge separation has also been developed and is in the process of being released. This will allow LCFI and other groups to investigate the physics made accessible at the ILC using the VXD including all experimental effects simulated in the detector concept’s Monte Carlo and reconstruction packages.

In the past year, the Linear Collider Flavour Identification (LCFI) Collaboration has taken significant steps towards having a sensor suitable for use in the silicon vertex detector of the International Linear Collider (ILC). The goal of the collaboration is to develop the sensors, electronic systems and mechanical support structures necessary for the construction of a high performance vertex detector and to investigate the contribution such a vertex detector can make to the physics accessible at the ILC. Particular highlights include the delivery and testing of both a second-generation column parallel CCD (CP-CCD), design of the next-generation readout ASIC (CPR2a) and a dedicated ASIC for driving the CP-CCD. This paper briefly describes these and other highlights.

We review the physics requirements for the ILC vertex detectors, which lead to the specification of silicon pixel sensors arranged as nested barrels, possibly augmented by endcap detectors for enhanced coverage of small polar angles. We describe how the detector requirements are a natural outgrowth of 25 years development of CCD-based vertex detectors in fixed-target and colliding beam experiments, culminating in the 307 Mpixel SLD vertex detector. We discuss how the technology has recently branched out into about a dozen architectures which might be made to work at the ILC, where the main challenge is to increase the effective readout rate by about a factor 1000 compared to conventional CCDs, while preserving the small pixels (∼20μm) and low-power dissipation. Preserving gaseous cooling as at SLD opens the door to layer thicknesses as low as 0.1% X0. Finally, we consider how best to manage electromagnetic interference associated with the beam wakefields and other RF sources during the bunch train. In conclusion, we suggest a strategy for moving on from the present rich R&D programmes to optimal detectors for the startup of the ILC physics programme.

Contributors: L Andricek, M Barbi, M Battaglia, A Bellerive, T Bergauer, G Bonvicini, S Boogert, D Bortoletto, J Brau, J-C Brient, D Chakraborty, P Checchia, D Christian, P Colas, W Cooper, P Dauncey, M Demarteau, Z Dolezal, G Eckerlin, R Frey, J Goldstein, J Hauptman, M Hildreth, P Karchin, D Karlen, Y Karyotakis, K Kawagoe, R Lipton, J List, W Lohmann, U Mallik, T Maruyama, K Moffeit, U Nauenberg, T Nelson, H Niemiec, Y Onel, A Para, H Park, R Partridge, D Peterson, M Piccolo, P Rehak, J Repond, K Riles, A Savoy-Navarro, L Sawyer, D Schulte, B Schumm, F Sefkow, R Settles, D Su, Y Sugimoto, A Sugiyama, E von Toerne, E Torrence, G Varner, I Vila, S Wagner, A White, R Wigmans, G Wilson, R Wilson, M Winter, H Yamamoto, F Zomer