The design of arithmetic circuits in beyond CMOS nanotechnologies has been of recent interest. Majority and minority gates, together with inverters, serve as the intrinsic logic primitives in a range of emerging nanotechnologies. Within the spectrum of high-performance addition schemes, parallel-prefix adder structures occupy a particularly prominent position. The design of efficient modulo $2^{n}-1$ adders is used in many applications. Therefore, efficient majority logic implementation of modulo $2^{n}-1$ parallel-prefix adders is highly desirable. In this work, majority logic implementation of existing parallel-prefix modulo $2^{n}-1$ adder architectures are presented and compared.

Beyond CMOS nanotechnology has been attracted interest by many researchers. The logical fundamental elements of many nanotechnologies are the majority, minority gates and inverters. The design of efficient adder systems and especially the parallel prefix adders is of very importance. In this paper efficient majority logic implementation of parallel prefix is introduced. The proposed methodology can be generalized to any parallel prefix structure design. Moreover, the proposed majority logic parallel prefix adder designs demonstrate decreased circuit complexity when compared to the literature.

Magnitude comparators are of great importance in modern high-performance systems. In this paper, we propose a new, efficient tree architecture for the full custom design of magnitude comparators in static CMOS logic. This architecture provides comparator designs with reduced propagation delay times and silicon area cost. According to extended simulation results, the propagation delay is equal or reduced by up to 13% with respect to state-of-the-art 64-bit, tree architecture, full custom design comparators. In addition, for the same 64-bit size, silicon area comparisons show an area reduction ranging from 8% to 21%. Overall, for the 64-bit comparator designs, the power-delay-area product is reduced from 12% to 26% when the proposed design scheme is adopted.

In this paper, investigation is performed on the design of efficient modulo 2n+1 adders, subtractors and add/ subtract units for weighted operands. The existing modulo 2n+1 adder, subtractor architectures are reviewed and compared. A new efficient modulo 2n+1 adder architecture for weighted operands is also presented. The proposed modulo 2n+1 adders and one of the existing most efficient modulo 2n+1 subtractors are combined into a modulo 2n+1 add/subtract unit. The proposed modulo 2n+1 add/subtract units exhibit decreased area and power complexity when compared to existing ones.

Digital magnitude comparators are used in digital systems to compare two binary numbers and to determine if the numbers are equal, or if one number is greater or less than the other. In this work the design of magnitude comparators in dynamic logic is examined. Two dynamic logic magnitude comparator designs are proposed and compared. One of these designs exploits an existing simplification, while the other is a totally new one. The new dynamic logic comparator design compared over the one based on the existing simplification, shows less hardware complexity, consumes less power and has lower power delay-product, for typical operand widths.

Majority, minority gates and inverters are the natural logic element of several beyond-CMOS emerging nanotechnologies. Magnitude comparators are components used in computer systems to compare if two binary numbers are equal or if one number is greater or less than the other. Therefore, efficient majority logic implementation of magnitude comparators is highly desirable. The proposed majority logic magnitude comparators have lower circuit and delay complexity compared against the already published majority logic magnitude comparator designs.

Digital comparators are important arithmetic components used in digital systems to determine if two numbers are equal, or if one number is greater or less than the other. In this work, the design of magnitude and 2's complement comparators is examined. New OR-based full tree and simplified tree magnitude comparator architectures are proposed. The existing and the proposed comparator architectures are implemented in standard cell technology and evaluated, after extensive experimental analysis, in high performance and relaxed conditions. The proposed comparators operate faster than the existing ones, while operating at the same speed yield significant improvement in area complexity and power dissipation.

In this work, the design of the diminished-1 modulo [Formula: see text] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [Formula: see text] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

Single Input Change (SIC) pairs, are pairs of patterns where exactly one bit flips between the two patterns of the pair and are valuable for the detection of robustly detectable stuck-open and delay faults. Therefore, the on-chip generation of SIC pairs has gained attention from a number of researchers. Previous schemes targeting the generation of SIC pairs utilizing adders affect the critical path of the adder, altering the timing characteristics of the circuit. In this paper a novel SIC pair generator is presented, based on a carry-look ahead adder. The proposed scheme imposes no intervention on the critical path of the adder, therefore its timing characteristics are not affected.

Single output functions have gained attention due to the popularity of FPGAs that implement complicated circuits based on Look-Up Tables (LUTs). LUTs implement single-output modules using multiplexer-based designs. In this work we present a scheme for the implementation of programmable single output functions. The proposed design can be utilized to implement LUTs with lower overhead compared to traditional designs with gate-based multiplexers.

Digital magnitude comparators are of special interest in digital systems as they are used to compare the magnitude (equality, greater than or less than) of two binary numbers. In this work, a new architecture for magnitude comparators in static logic is presented. The proposed topology presents superior speed performance and reduced power consumption (that improve as the size of the comparator increases for comparators greater than 8bit) with respect to a state of the art magnitude comparator in the literature.

In this work we present a low cost Boolean function generator based on the use of a decoder with tri-state outputs.

Complex arithmetic operations dominate Digital Signal Processing (DSP) applications heavily degrading their performance. Targeting to accelerate the Residue Number Systems-based DSP applications, we optimize the design of the Add-Multiply (AM) operation with modulo 2n + 1 diminished-1 operands by incorporating the direct recoding of the sum of two numbers in its Modified Booth form. Compared to the conventional allocation of an adder and a subsequent multiplier, the proposed fused AM design yields delay, area and power gains.

The 2's complement representation is widely adopted, since compared to the other signed number systems has the advantage of simpler addition and single representation of zero. Sing-magnitude representation is used in digital signal processors for the representation of digital signals for low-power purposes. The 1's complement representation compared to the 2's complement one has the advantages of the simpler conversion to and from the sign-magnitude representation, simpler negation and that truncation of negative numbers is equivalent to that of the sign-magnitude representation. Therefore, the design of efficient arithmetic units for this system should be examined. In this work 1's complement modified Booth multipliers with complexity similar to that of the 2's complement ones are proposed.

In this work we propose a new technique for the generation of binary functions based on the use of a decoder with tri-state outputs. The hardware overhead of the proposed scheme compared to other generic schemes like the multiplexer-based and decoder-based implementation is significantly lower.

Digital Signal Processing (DSP) applications are dominated by complex arithmetic operations, which heavily degrade their performance. Targeting to accelerate the execution of Residue Number Systems (RNS)-based DSP applications, in this work, we focus on optimizing the design of the modulo 2 n + 1 Add-Multiply (AM) operation with weighted operands. We incorporate in our design a new direct recoding of the modulo 2 n + 1 sum of two weighted operands in its Modified Booth form. Compared to the conventional design of first instantiating an adder and then, driving its output to a multiplier, the proposed fused AM design yields considerable delay, area and power gains.

Two modified architectures for modulo 2n+1 adders are introduced in this paper. Only some of the carries of modulo 2n+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing stage and carry select blocks are combine the multiplexer operation of a diminished-one adder can be implemented in smaller LUT's and less consumes power, while maintain the same operating speed and delay. The modulo adder 2n+1 adders can be easily derived by adding extra logic of modulo 2n-1 adders present in second architecture.

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of Single Input Change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper a software-based implementation for the generation of SIC pairs is presented.

Input vector monitoring concurrent Built-In Self-Test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit off-line in order to perform the test. In this work we present an input vector monitoring concurrent BIST scheme, specially designed for the testing of ROM modules.

In this work an algorithm for embedding test sets containing don't care values into sequences generated by binary counters is utilized and evaluated. Furthermore, a simple, yet effective, technique to decrease test application time is explored. Experiments carried out on ISCAS benchmarks reveal that the proposed scheme results in considerably shorter test sequences.