Cache memory is a critical resource for performance, and as is well known, faults in it can significantly impact processor efficiency. In our everyday life, in non-critical real-time applications, it is desirable for quality of service that performance remains high, and that the worst-case execution time is as close to the average as possible. In this paper, we demonstrate that neither disabling only the faulty cache sub-blocks [1] nor disabling entire blocks that contain at least one faulty sub-block [23] yields optimal results in terms of average performance and performance variance in faulty CPU caches. Instead, we show that selectively disabling blocks with more than N faulty sub-blocks, while disabling only the faulty sub-blocks in all other blocks, leads to better average performance and lower performance variance. The optimal value of N depends on both the fault percentage and the granularity of the sub-block.

The aggressive reduction of the supply voltage, aiming for ultra-low power operation, affects the reliability of ICs and especially the memory structures (SRAM cells). Furthermore, the increasing usage of real-time applications into various facets of our daily lives has emphasized the necessity for predictable execution times of applications operating on these systems. In this work, we study the impact of defective first-level data caches (DL1) on system performance and its performance fluctuation. Based on analysis, we propose new fault-tolerance mechanisms that are able to mitigate the average performance degradation and at the same time, to reduce the performance deviations from the average value increasing this way the performance predictability. Our gem5-based evaluation results across a wide range of percentages of malfunctioning cells, a plethora of fault maps and the benchmarks from the Worst- Case-Execution-Time (WCET) suite show that the proposed mechanism achieves its purpose.

Reducing the supply voltage in today′s process technologies introduces significant reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance (CFT) techniques have been developed to ensure error free and performance efficient execution in the presence of faults. A class of recent CFT techniques are based on the concept of disabling cache portions, such as (sub-)blocks or words that include defective bits, and reconfiguring operational ones (e.g., physical or logical neighbor (sub-)blocks). All those techniques require significant circuit modifications which may pose unacceptable overheads to time-sensitive L1 caches. In this work we propose to deal with the cache reliability problem at a very different level. We assume that faulty caches are enhanced with the ability of disabling their defective parts at different sub-block granularities. The key idea is to leverage the spatial reuse patterns of the memory blocks (not all the data fetched into the cache is accessed) in order to mask out the additional, due-to-faults, cache misses. To this end, we propose a new class of frugal spatial predictors (with 24-bytes storage requirements) to orchestrate the replacement decisions of the fully and partially functional cache blocks. Our evaluation results reveal that the proposed approach is able to offer 32.3% on average, among all studied percentage of failures, increase in hit ratio in first level data caches (64.6% in instruction caches) over a conventional faulty cache (based on block disabling). Further, experimental results reveal the superiority of the proposed method with respect to Instructions-Per-Cycle and Energy-Delay-Product.

As the technology continuous to shrink, power consumption appears to be the main design parameter. Operation on low voltage negatively affects mainly the operation of on-chip memories, resulting in multiple malfunctioning memory cells. As a reaction many cache fault tolerance (CFT) mechanisms have been proposed targeting the mitigation of performance degradation. The challenge is to devise mechanisms that are tailored to the memory access patterns of the executing applications. In this work we initially investigate the impact of the granularity of cache line disabling scheme in the first level data caches. Based on our analysis, we propose a run time adaptive mechanism that is able to opt the cache (sub-)block taking into account the diverse memory characteristics of the application. The proposed mechanism is based on the widely used block (sub-block) disabling scheme, and dynamically selects the appropriate sub-block granularity during the execution of the applications. Our evaluation results reveal that the proposed dynamic approach is able to offer significant benefits over a faulty cache design with a monolithic (sub-)block granularity.

Aggressive dynamic voltage and frequency scaling is widely used to reduce the power consumption of microprocessors. Unfortunately, voltage scaling increases the impact of process variations on memory cells resulting in an exponential increase in the number of malfunctioning memory cells. As a result, various cache fault-tolerant (CFT) techniques have been proposed. In this work, we propose a new CFT technique which applies a systematic redistribution (permutation) of the cache blocks (assuming various block granularity levels) within the cache structure using the orthogonal Latin Square concept and taking as input the location of the malfunctioning cells in the cache array. The aim of the redistribution is twofold. First, to uniformly distribute the faulty blocks to sets and second, to gather the faulty subblocks to a minimum number of blocks, so as the fault free blocks are maximized. Our evaluation results using the benchmarks of SPEC2006 suite, 100 memory fault maps, and four percentages of malfunctioning cells show that our proposal exhibits strong capability to reduce cache performance degradation especially in situations with high percentages of faulty cells and compares favorably to already known techniques.

Single event transient (SET) pulses are a significant cause of soft errors in a circuit. To cope with SET pulses, we propose a new storage cell that is able to operate either as a hard-edge or soft-edge flip-flop depending on the appearance or not of a transition in a time window. The efficiency of the proposed design with respect to the reduction of soft-errors coming from SET pulses was shown with extensive simulations.

Two modified architectures for modulo 2n+1 adders are introduced in this paper. Only some of the carries of modulo 2n+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing stage and carry select blocks are combine the multiplexer operation of a diminished-one adder can be implemented in smaller LUT's and less consumes power, while maintain the same operating speed and delay. The modulo adder 2n+1 adders can be easily derived by adding extra logic of modulo 2n-1 adders present in second architecture.

In this paper we first present a new test vector multi-bit correction technique for capture power reduction (average and peak) in scan based launch-on-capture transition delay testing of IP cores. Then we present a method which combines the test vector multi-bit correction technique and the dictionary based test data compression method of [11] in order to derive compressed test data with low capture power. Main characteristic of this technique is that the reduction of the capture power is obtained without (or with marginal) degradation of the compression efficiency. The efficiency of the proposed method is verified with simulations.

Since Arduino is the main entry-level platform to the world of electronic circuits and systems, there are many programming environments that try to ease the burden of Arduino textual programming on young primary students. Although block-based, most of these environments retain the imperative structures of textual programming languages, which are not easily comprehensible by such students. The proposed, in this paper, Learning-Arduino-With-Rules Introductory System (LAWRIS) tries to tackle this problem by adopting a rule-based approach: an Arduino-based pre-specified system can be programmed by constructing rules with very simple and intuitive jigsaw pieces, in a visual, web-based environment. Contrary to other programming environments for Arduino, the main logic of LAWRIS is implemented on the board side and only a configuration string is downloaded to it. Thus, LAWRIS features fast responses to both circuit input changes and program modifications, a very important characteristic for young students. It also imposes minimal overhead on the host system, allows web access of the programming environment, and has very low hardware cost.

Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management technique. Unfortunately, voltage scaling increases the impact of process variations on memory cells reliability resulting in an exponential increase in the number of malfunctioning memory cells. In this work, we systematically investigate the behavior of branch target buffers (BTB) with faulty memory cells. Although being an intrinsically fault-tolerant unit (i.e., it does not affect correctness of the system), as we show in this work for several fault probabilities and core configurations, disabling the faulty parts of BTBs can damage the performance of the executing applications. To remedy the negative impact of malfunctioning BTB memory cells in contemporary BTB organizations, we present an ultra lightweight performance recovery mechanism. The proposed mechanism introduces minimal hardware overheads and practically-zero delays. Using cycle-accurate simulations, the benchmarks of SPEC2006 suite, a plethora of memory fault maps, and two fault probabilities corresponding to low supply voltages, we show the effectiveness of the proposed recovery mechanism.

Processor caches play a critical role in the performance of today"s computer systems. As technology scales, due to manufacturing defects and process variations a large number of cells in a cache is expected to be faulty. The number of faulty cells varies from die to die and in the field of the application depends on the operating conditions (e.g., supply voltage, frequency). Several techniques have been proposed to tolerate faults in caches. A drawback of the redundancy based techniques is that the amount of redundancy is decided at the design time targeting a maximum number of faults, so in cases of a small number of faults (e.g., in the nominal supply voltage in a system with DVS) only a part of the redundant resources is used. In this paper we propose a new reconfigurable-self adaptive fault tolerant cache scheme. The unique characteristic of our scheme is that it uses its resources for both the reduction of the misses caused by the faulty blocks as well as for the reduction of conflict misses, depending on the number of faults, their distribution in the cache, and the running application. Our experimental results for a wide range of scientific applications and a plethora of fault maps with different SRAM failure probabilities reveal that our proposal can achieve significant benefits.

Test data volume is now recognized as a major contributor to the cost of SoC manufacturing testing, as it leads to an increasing testing time. In this paper we present the progress of the dictionary based test data volume reduction (compression) methods.

Operating below nominal voltage levels is a promising direction to enable ultra-low power CMOS-based sytems. This is true due to the cubic relation between the dynamic power consumption and the supply voltage. The main roadblock during aggressive voltage scaling is that the reliability of the circuits and especially of memory structures (SRAM cells) is exponentially decreased. The usage of well-known error correction codes (ECC) can only remedy a part of the problem. ECC have been proposed to protect the lower level caches (e.g., L2 or L3), but ECC cannot be employed in single-cycle first level caches due to their performance sensitivity to the additional latency of ECC. In this work, we propose a methodology to solve this problem by exploring the use of criticality metrics in aggressive superscalar processors. Instead of disabling the faulty frames of a faulty cache (as proposed in related work), we keep these frame alive (data are still placed and accessed in these faulty frames) and we use strong ECC to correct the hard multibit errors. The key idea is to direct to faulty cache frames data that can be delayed for one or more cycles without affecting program completion time i.e., instructions considered to not be on the critical path of the program execution. The basic mechanisms for hardening first level faulty caches with strong ECC protection without inflating program executing time are described in this position paper.

One-time factory testing of VLSI components after fabrication is insufficient in the deep submicron era. The products must be tested periodically in the field of application. Due to the complexity of the Systems on a Chip (SoCs), huge amounts of test data are required. However in many embedded systems the capacity of the available memory is a limited resource. Besides in real time embedded systems the in-field testing activities should be accommodated with the real-time constraints of the system. In this paper we at first show the suitability of the LFSR-based Test-Data Compression with Self-Stoppable Seeds method [10] for in-field testing and we give the required enhancements so that can be used as a Preemptive Built-In Self-Test mechanism for in-field testing that is applied at the idle time intervals of a hard real-time embedded system with sporadic tasks. Then, based on a probabilistic model and extensive simulations, we show that in the proposed method the time required to apply all the test vectors to the Circuit Under Test is many times smaller than the time required when the testing procedure consists from one or more non-preemptive test sessions. The proposed method achieves lower energy consumption for testing and significantly smaller fault detection latency times.