This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.

A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise figure of 6.5-8.4 dB across three bands, and a TX 1-dB compression point of -10 dBm. The circuit consumes 105 mW from a 1.5-V supply.

This paper presents a single chip dual-band transceiver, fully compliant with the IEEE 802.11 a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error-vector-magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5 dBm and the receiver sensitivity is better than -70 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.

A 0.18μm CMOS transceiver fully compliant with IEEE 802.11a in the U-NII band (5.15 - 5.35GHz) achieves a sensitivity of -69dBm and an EVM of -29.3dB for 64 QAM. Power dissipation is 171 mW in RX and 138mW in TX using a 1.8V supply.

A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz) achieves a receiver sensitivity of -5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of -29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18-/spl mu/m CMOS and operating from 1.8-V power supply, the design consumes 171 mW in receive mode and 135 mW in transmit mode while occupying less than 13 mm/sup 2/.

This paper describes the design of a CMOS frequency synthesizer targeting wireless local area network applications in the 5 GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2 GHz output as well as the quadrature phases of a 2.6 GHz carrier. Fabricated in a 0.4 /spl mu/m digital CMOS technology, the circuit provides a channel spacing of 23 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz at 10 MHz offset. The reference sidebands are at -50 dBc at 2.6 GHz and the power dissipation from a 2.6 V supply is 47 mW.

New wireless local area network (WLAN) standards have recently emerged in the 5 GHz band. For example, high performance radio LAN (HIPERLAN) is a European standard operating at 5.2 GHz with Gaussian minimum shift keying (GMSK) modulation and a 23 MHz channel bandwidth. The voltage-controlled oscillator reported here is to be used in a HIPERLAN transceiver. Here, the receiver employs two downconversion steps, each with a 2.6 GHz local oscillator (LO) frequency, translating the RF spectrum to dc. The second downconversion thus requires the quadrature phases of the LO. The transmitter performs modulation by first placing the VCO in a synthesizer loop and subsequently opening the loop and applying the Gaussian-shaped baseband data to the VCO to perform GMSK modulation.

This paper presents a single chip dual-band transceiver fully compliant with the IEEE 802.1 la/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805