Novel Cu via interconnects connecting Cu redistribution lines (RDLs) was proposed as advanced fan-out chip on substrate (FOCoS) technology for high-density packaging. The advance in downsizing Cu interconnect structure causes a rising concern for electromigration reliability. In this study, the electromigration behavior and failure mechanism in a novel 3D Cu stack-via interconnect were reported for the first time. The Cu stack-via structures, composed of three vertically stacked Cu microvias, were subjected to electromigration experiments at 5.1 x 105 A/cm2 at 180 degrees C with opposite electron flow directions to investigate the anisotropic electromigration behavior on the microstructure and electrical performance. Divergent electromigration behavior was disclosed in the Cu stack-via with different electron flow directions. The failure mechanism of the upstream Cu stack-via was governed by a rapid electrical resistance rise at the end of current stressing due to the synergistic local current crowding and Joule heating effects, and the volume shrinkage due to phase transformation further caused the open-circuit failure. The failure mechanism of the downstream Cu stack-via was governed by a gradual electrical resistance rise due to the depletion of Ni diffusion barrier metallization and the subsequent Cu microvia phase transformation to high-resistivity Cu-Sn IMC phases. In this study, the design rules of the Ni metallization thickness required to prevent early Ni metallization depletion and the Cu stack-via configuration to prevent local current crowding for improved electromigration reliability will be investigated for further progress in the novel 3D Cu stack-via interconnect development.

Effective heat dissipation is crucial for maintaining high performance and reliability of microelectronic devices. This study examines the thermal performance of vapor chambers featuring various hierarchical dendritic wick structures. The capillary wicks, featuring different dendritic morphologies and thicknesses, are fabricated on high-strength cupronickel alloy substrates using electrodeposition and sintering processes. The optimal capillary performance value (K/Reff) of the featured wick structure is 1.34 mu m. The wick's multiscale porous structure facilitates liquid circulation, liquid/vapor phase-change efficiency, and vapor transport capability in the vapor chamber device. The diffusion-bonded vapor chamber devices, charged with different water-filling ratios, achieve a remarkably low thermal resistance of 0.056 degrees C/W at a heat load of 500 W and can operate effectively under 800 W. The vapor chamber device with hierarchical dendritic wicks stands out from traditional heat dissipation devices with sintered powder, mesh, and grooved wicks regarding capillarity and thermal performance, making it highly effective for dissipating heat from concentrated sources. This study will contribute to the development of vapor chamber technology for high-power heat dissipation applications.

In this study, we introduce a design of a dual-band (28/39GHz) 1x4 antenna array on a 14(6+2+6) multi-layer organic substrate. The design aims to achieve dual-band and higher isolation within a compact 3.8x23mm(2) AiP module. This paper introduces a novel antenna design utilizing a frequency selective surface (FSS) on a multi-layer organic substrate to achieve compact size and dual-band antenna for 5G mobile applications. The proposed antenna comprises a low-band (LB) and high-band (HB) element, with the HB element positioned coaxially beneath the radiator of the LB element to minimize overall size. The LB element features a double-layer FSS-based antenna and differential pairs of feeding probes, while the passband of the FSS-antenna is designed to cover the operating band of the HB element, enabling transmission of HB element radiation through the FSS-radiator of the LB element. A prototype of the dual-band antenna, operating in the LB frequency range of 26-29 GHz and the HB frequency range of 39-43 GHz, showing high gain of approximately 10 dBi in the LB and 12 dBi in the HB within a compact AiP module of 3.8x23 mm(2). The proposed antenna is designed for ease of fabrication and cost-effectiveness, making it suitable for mmWave 5G smartphone with support multiband applications.

In advanced packaging products, fan-out structures provide superior performance but exist challenges due to the mismatch in the coefficient of thermal expansion (CTE) between copper and polymer layers, increasing the risk of delamination. In this study, we compare the adhesion strength of copper-polymer interfaces using the stud-pull test and the double cantilever beam (DCB) method. The results show that the studpull test exhibited intralaminar fractures within the material or fracture between the stud and the experimental samples, while the DCB method provides more efficient adhesion strength measurements. Therefore, we recommend using the DCB method to better evaluate copper-polymer interfacial adhesion strength before RDL designs and manufacture, reducing the time and cost of material selection and testing.

The increasing demand for high-performance computing (HPC) has driven processor designs toward chiplets integration and ASIC-HBM architectures using high density interconnection technology. While wafer-level fan-out packaging (FOWLP) has become a widely adopted solution for such applications, it faces challenges including warpage control, complex processes, and carrier utilization limitations. To address these challenges, panel-level fan-out packaging (FOPLP) has emerged as a promising alternative. FOPLP offers a higher carrier utilization ratio than waferlevel processes, enabling improved material efficiency. Additionally, panel-level manufacturing can deliver higher throughput by reducing handling and transfer time, potentially offering cost advantages and improved scalability. This paper presents the development of a 300 mm panellevel fan-out (FO) solution for chiplets integration in HPC applications. The study compares the panel utilization efficiency in large reticle-sized designs versus traditional 300 mm wafer-level fan-out solutions. To further enhance patterning precision in panel-level processing, a novel Laser Direct Imaging (LDI) technique was implemented. Meanwhile, the key factors influencing panel warpage, chip-on-panel solder joint integrity, and process optimization were also investigated. The results demonstrate a successful implementation of Fan-Out Chip Last technology in a 300 mm panel platform, achieving higher density, larger module size, and improved reliability. These advancements make 300 mm panel-level fan-out an attractive solution to meet the evolving demands of nextgeneration HPC and AI applications.

To accomplish a higher I/O density in advanced IC packages, the requirement of Cu redistribution lines (RDL) with finer pitch of line/space rapidly increased. While the shrinkage of cross section of interconnects enhanced the space utilization in IC package, the resulting increase in current density will intensify the electromigration and eventually threaten the reliability of IC packages. The present study focused on building a numerical Cu RDL model that can demonstrate its electrical performance under an electric current stressing test. In order to bring more experimental information into the numerical Cu RDL model, a procedure to transfer microstructural features of interconnect to the numerical model was established and successfully revealed the diverse performance in electrical resistance between samples comparing to those data collected from current stressing test.

Fan-Out-Chip-on-Substrate (FOCoS) is an advanced packaging technology to meet the demanding of high-performance computing (HPC) and artificial intelligence (AI) applications. FOCoS-Bridge is a key enabler for achieving high die-to-die and die-to-memory connectivity while addressing the large reticle size challenges in silicon interposer technology. To support the increasing demand for larger bandwidth, higher I/O density, improved power delivery, and enhanced thermal dissipation in future HPC and AI products, we introduce "FOCoS-Bridge with TSV" as an advancement to ASE's VIPackTM FOCoS-Bridge technology. This enhancement integrates a bridge die featuring a specialized Through Silicon Via (TSV) structure to provide better electrical performance and improved heat dissipation. In this paper, the FOCoS-B with TSV test vehicle was built-up and it was composed of two identical fanout assembled on a single FCBGA (Flip Chip-Ball Grid Array) substrate in MCM (multichip-module) arrangement. Each of fanout module was integrated by 1 ASIC and 4 HBM3 with 4 TSV-bridge dies and 10 IPD (Integrated Passive Devices) dies. Total 14 dies were embedded within a FO module and the Fanout module size is similar to 1.8x reticle size (similar to 1500mm(2)). The package body size is 85mm x 85mm. Meanwhile, the warpage behavior in large FO module and assembly processes were investigated. The impact of different assembly techniques including mass reflow (MR) and thermocompression bonding (TCB) on solder joint quality was also studied. The results demonstrated that TCB assembly effectively enabled the successful integration of FOCoS-Bridge with TSV and embedded IPD, achieving superior performance and reliability. This enhanced packaging solution addresses the evolving demands of next-generation HPC and AI applications and offering improved scalability and integration capabilities.

The research and discussion in this paper, there are package design with the structure of FOCoS (Fan Out Chip on Substrate) for an actual high-performance computing IC device with one ASIC (Application Specific Integrated Circuit) chip and two HBM3e (High Bandwidth Memory) chips. In the process of this study, the interface of HBM3e memory is applied on data transfer between ASIC chip to high bandwidth memory. Through stress and electrical analysis, the suitable RDL (Re-Distribution Layer) structure and routing topology are used to ensure process yield.

With the development of the science and technology industry, the trend of miniaturization and multi-function integration in handheld and head-mounted smart glasses has become a more popular topic, in case of devices dropped from a high place will suffer severe acceleration (G) generated by mechanical impact to ground, owing to its body configuration of higher integration density and heavier weight. Meanwhile, the inside electronics might be solder joint damaged because the stresses exceed its solder material ultimate strength, and the electronic motherboard plays an important role of transmission buffer under shock energy. Therefore, board level shock reliability test is taken into account to ensure products quality before the mass production, and industries seek to realize the precisely reliability life prediction methods. In this paper, firstly we focus on the PCB (Print Circuits Board) with 2:1 aspect ratio, attach strain gages to measure the in-plane behaviors and PCB peak deformation in shock duration, acceleration range of 1,500G to 10,000G are taken into consideration with recording the specific shock height, further link the response data into the nonlinear oscillation methodology to come out the equation parameters. The following FEM (Finite Element Method) electronics life prediction model will be cited and verified in accuracy enhancement. In order to deeply understand the PCB instant shock phenomenon, we introduce a high-speed photography technology to conduct non-contact measuring analysis under 10,000G shock energy, obtain PCB out-of-plane peak deformation value, oscillating waves and dynamic shapes. In addition, we show the relationship of PCB dynamic viscous damping system, natural frequencies, accelerations and damping ratios. Finally, this study found out the PCB damping ratio 86% highly increasing from 1,500G to 10,000G. Displayed the achievement of modified FEM constitutive model uses in ANSYS LS-DYNA, accurately approach PCB dynamic behavior, narrow the calculation errors of electronics solder joint life prediction on shock reliability.

This study provides an in-depth simulation of the capillary underfill (CUF) process for flip-chip packages using Moldex3D, offering a comprehensive analysis that integrates material properties, process parameters, and structural factors within a unified framework. The material properties explored include viscosity and reaction kinetics, while the process parameters focus on controllable factors such as resin temperature, mold temperature, dispensing start time, dispensing weight, and dispensing end time. Structural parameters like bump pitch and gap height are also studied. The study further validates its findings with experiments conducted on a high bump count of 1530, showing that the experiment and simulation results are consistent. Key findings reveal that a larger die pitch accelerates the filling process, the incorporation of edge channels enhances filling efficiency, and optimizing the dispensing path improves flow uniformity. Adjusting the dispensing weight and intervals can mitigate edge effects and tongue spreading. Regarding material properties, higher surface tension and lower contact angle significantly increase filling speed, though they have a minimal impact on the overall flow pattern during the underfill filling process. These insights are crucial for optimizing the CUF process, ultimately improving the reliability and performance of flip-chip packages.

The warpage performance of the fan-out wafer for chip-first processes is investigated by the finite element modeling in this study. In the modeling framework, which including the element birth-and-death technique for molding material removal and effective properties calculated for the copper layers of RDL, is used to determine the warpage evolution at different process stages. The developed FE simulation method can well describe the wafer process warpage. Therefore, the effect of different structure dimensions on wafer warpage prediction can be conducted.

This study attempts to study the two-phase immersion cooling for the FOCoS HPC package subject to a power input of up to 1000 W which hasn’t been reached before. It explores two approaches: an enhanced boiler surface integrated with the HPC package and a heat pipe heat spreader integrated heat sink. Two-phase immersion cooling is an effective method to meet the exponentially increasing demands of thermal loading of high-density electronic devices. At high chip thermal densities, effective heat spreading along with heat dissipation is paramount to avoid overheating. The current study utilizes a heat pipe spreader integrated with the heat sink, which ensures that the heat properly spreads toward the heat sink base before it can be effectively removed by the fluid through phase change. A simple enhanced boiler surface integrated with the HPC package is also considered for comparison in this study. A multiphase CFD model is developed in ANSYS-Fluent with Eulerian treatment of the two-phase flow employing the RPI boiling model for phase change. The numerical model is validated against the experimental results for boiling over a plain surface with a maximum deviation within ±10%. The numerical results show that the heat sink integrated with a heat pipe heat spreader is capable of maintaining junction temperature well below 105 °C at a TDP of 1000 W.

The present study adopted in-situ SEM to investigate the electromigration behavior of fine line Cu RDL, 2 μm (width) x 3 μm (thickness) x 20 μm (length), especially focusing on the void migration and the effect of PI passivation on suppressing electromigration. The electromigration were conducted at high current density (10 6 A/cm 2 ~ 3.06 x 10 7 A/cm 2 ) and 77~100°C (heat plate). A critical current density of 1 x 10 7 A/cm 2 was identified below which no electromigration occurrence was observable on the bare Cu RDL. Hillocks accumulated at the anode side at above 1.5 x 10 7 A/cm 2 . Voids were generated and grew on the cathode side at the triple joint of grain boundary. The in-situ video revealed that the void started migrating towards the anode after growing up to around 0.3 μm. The void was seen moving rapidly within a large grain, while hindered by grain boundary when hit smaller grains. With the kinetic information captured from the in-situ video, the migration flux as well as the diffusion coefficient was calculated. The diffusion coefficient was estimated to be 3.95~7.85 x 10 -10 cm 2 /sec and 1.68 x 10 -9 ~ 1.04 x 10 -8 cm 2 /sec at the low (227°C) and high (333°C) circuit temperatures estimated with temperature coefficient resistance, respectively. Electromigration experiment of the PI passivated Cu RDL showed that no hillock was observable at the anode side after current stressing.

In this paper, we introduce a compact 28GHz 1x4 antenna array featuring shorted parasitic elements, designed on a 10(4+2+4) multi-layer organic substrate. This allows for a broad bandwidth in a compact Antenna-in-Package (AiP) module. While Microstrip patch antennas are favored in AiP for their low profile, ease of fabrication, cost-effectiveness, and seamless RF chip integration, they typically exhibit drawbacks like narrow bandwidth and diminished gain. An established solution to counter these limitations involves the use of stacked patch antennas with parasitic elements, which enhance impedance bandwidth and gain. Yet, this comes at the expense of a larger AiP footprint and cost, posing integration challenges in mobile devices and complicating mechanical designs. To address the size constraint, we introduce a novel design: a stacked patch antenna incorporating shorted parasitic elements. This innovative design uses smaller parasitic elements but doesn't compromise on performance. By grounding the parasitic elements appropriately, a short-circuit mirror-image current effect is realized, leading to a reduced component area. Post-optimization, the size is refined from 6.5 x 25 mm 2 to 4.5 x 25 mm 2 , marking a 31% reduction. Performance-wise, simulations reveal a return loss exceeding 10 dB within the 25-30 GHz spectrum, about 5 GHz bandwidth, and a high-gain per element radiation pattern (over ~6 dBi) suitable for 28GHz applications. Further, a 28GHz beamforming array is detailed, incorporating a four-channel transceiver with a 1 x 4 antenna array. For active testing, we designed an integrated socket and load board to support the mmWave module, bridging the Device Under Test (DUT) and the test system. The load board substrate is segmented to manage the IF, LO, and DC distribution networks. There's also a four-channel transmit beamforming array front-end module earmarked for design. The paper culminates by showcasing the 3D beam steering capabilities of the 1x4 antenna array across multi-states at 28 GHz, achieving a peak gain of 11 dBi in the primary beam direction. Our results affirm that by manipulating the signal phase in individual antenna elements, beamforming can be oriented towards a precise direction. The beam steering range spans approximately 75 degrees. This compact antenna design offers both bandwidth and size advantages, making it an attractive solution for 28GHz mmWave bands in mobile devices, specifically for n257, n258, and n261 channels.

During the capillary underfill (CUF) process in flip-chip packaging, issues like incomplete filling, voids, wire sweeping, and overflow can impact product reliability and the relatively long filling time required. Therefore, finding ways to improve filling efficiency is a critical challenge. Conducting experiments to address these issues can be costly. As a result, the industry often relies on simulation software to simulate the actual manufacturing process, predict potential problems, compare results with experimental data, and analyze ways to improve the process. This approach helps enhance the package yield and further improves production efficiency.This study investigates the capillary underfill (CUF) process through simulation. Firstly, the viscosity and reaction kinetics of the underfill material are measured to establish the necessary data for the simulation. Then, Moldex3D, a mold flow simulation software, is used to create the model, generate the mesh, and perform the process simulation analysis. The effects of material properties and process parameters on the capillary underfill process are considered. The simulation results are compared with experimental data to validate the feasibility of the simulation. Subsequently, different flip-chip package structures and CUF process parameters are analyzed through simulation to explore the impact of these parameters on the flow pattern and filling efficiency of the adhesive material during the filling process.According to the simulation results, the filling speed is faster when the bump pitch and gap height are larger. However, the required filling time still has a considerable relationship with the volume of the filling region. Dispensing from the side with lower bump density can shorten the filling time when the bump distribution is uneven.

In this study, flip-chip quad flat no-lead (FCQFN) solder interconnects with various metallization combinations were investigated for the electromigration study. The effects of Ni and Ag metallizations on the interfacial reaction and electromigration failure behavior of the solder interconnects were investigated. Direct current input of 2 A (approximately 1.0 × 10 4 A/cm 2 ) was applied to the solder interconnects at 160°C for a period achieving 200%-electrical-resistance-increase as a failure criterion. The additional incorporation of Ni metallization at the Cu pillar/Sn1.8Ag interface suppressed the growth of Cu-Sn IMCs at the interfaces, resulting in the remaining Sn1.8Ag solder matrix after electromigration. The predominant (Cu,Ni) 6 Sn 5 IMC was formed at the interfaces, preventing the undesirable Kirkendall void formation in the CU 3 Sn phase. The polarity effect occurred in the solder interconnects with a thicker IMC on the anode side. The additional incorporation of Ag metallization at the Sn1.8Ag/Cu lead frame interface and the subsequent Ag3Sn IMC formation have a limited effect on suppressing interdiffusion and inhibiting the formation of CU 3 Sn IMCs on the Cu pillar or Cu lead frame side, regardless of the electron flow direction. The results presented in this study offer insights for optimizing solder interconnect design by selecting appropriate metallization combinations to mitigate electromigration-induced failures.

In this study, we reported direct observation of void nucleation and growth in a fan-out 2-µm-wide Cu redistribution line (RDL) embedded in polyimide dielectric layers using in situ scanning electron microscope (SEM) investigations. The electromigration experiment was conducted with an extremely high current density of $1.14 \times 10^{7}\mathrm{A}/\text{cm}^{2}$ under an ambient condition. Current stressing induced the nucleation, growth, and coalescence of nanovoids on grain boundaries. Nano-scale delamination at the local Cu oxide/Cu RDL interface occurred. The electromigration-induced reliability challenge correlated with the void evolution in the Cu RDL was reported for the failure behavior and mechanism.

Power module market has grown significantly in recent years. In the power module structure, thicker mold thickness, wire diameter and higher arc height are required. However, during the actual production process, there are different influencing factors that lead to some production defects, such as short shots, voids and wire sweep, etc. For the purpose of improving product reliability, it is necessary to take some effective methods to reduce such production defects. The main purpose of this research is to use the mold flow tool to predict the racing effects and encapsulation problems of epoxy molding compound (EMC) caused by different product geometry, processing conditions and material properties during the molding process and offer an optimal solution for power module. By changing the gate layout, position and materials, we can effectively reduce void defects and wire sweep percentage during the molding process.

Polymer compounds including epoxy molding compound and underfills are widely used in high-performance multi-die package designs. In addition to the issue of thermal expansion mismatch to Si dies, the moisture absorbing nature of these compounds leads to hygroscopic swelling, interface adhesion degradation, and vapor pressure build up at high temperatures. In this study, the debonding of Si-underfill interface in a fan-out package was considered by using fracture mechanics approach. The interface fracture toughness was first measured by using four-point bending test. A numerical procedure was implemented as finite element post-process for vapor pressure calculation. Virtual crack closure procedure was applied to evaluate the crack driving force under hygro-thermo-mechanical load at reflow condition. Failure driving forces associated with vapor pressure, thermal expansion mismatch and moisture swelling were compared. The results indicate that the Si-underfill debond driving force at the Si-sidewall is significantly higher if vapor pressure is present.

In the capillary underfill packaging process, resin with specific characteristics such as low viscosity, high flowability, fast curing, and high reliability is utilized to fill the gaps between the substrate and the die. This underfill resin serves to reinforce the connections between metal bumps and the substrate, thereby extending the lifespan and enhancing the reliability of FCBGA (Flip-Chip Ball Grid Array) packages. Despite the availability of flow simulation tools, the development of the underfill process remains a significant challenge for engineers due to the multitude of control parameters involved. The objective of this study is to identify the key factors influencing the accuracy of underfill flow simulations and explore potential solutions to these challenges. In this study, it is found that necessary ingredients for accurate underfill simulation need to include the following items: 1. Good flow simulation software 2. Accurately measured material properties 3. Good and fine mesh 4. Right amount of dispensed resin 5. Right timing for resin dispensing. The accuracy of the simulation is particularly affected by factors such as overflowing, resin climbing, non-uniform flow, and air trapping, which are influenced by the amount and timing of resin dispensing. By addressing these factors, this study demonstrates that accurate underfill simulation can be achieved, providing valuable insights into microscale flip-chip underfill physics. This research lays the groundwork for the development of validated models applicable to next-generation high-density flip-chip products.