This paper presents the design and measurement of a Q-band low-noise amplifier (LNA) fabricated in a 0.13 μm SiGe BiCMOS technology. The proposed LNA employs a cascode topology and achieves a minimum noise figure (NF) of 1.78 dB and a measured peak gain of 15.7 dB at 36.5GHz over a 3-dB bandwidth of 20GHz. The measured input-referred 1-dB compression point is IP1dB= -12.5 dBm and the measured input-referred third order intercept point is IIP3= 6.7 dBm. The LNA exhibits an excellent figure of merit (FOM) of 9.34, which to the authors’ knowledge, significantly outperforms previously published Q-band LNAs. The circuit consumes 36.73mW of DC power from a 3.3V supply and occupies a total chip area of 0.18 mm2, including pads.

This work presents a 240–270-GHz transmitter array implemented in a 0.13- $\mu $ m SiGe BiCMOS process. The transmitter array comprises two J-band $\times 6$ frequency multipliers, four J-band four-way combined power amplifiers (PAs), and an on-chip $2 \times 2$ antenna array. The system is driven by an external continuous-wave (CW) signal generator, and each four-way combined PA delivers a peak output power of 16.7 dBm at 250 GHz with a 3-dB bandwidth of 50 GHz. The integrated antenna array consists of four differential dipoles with a reflector layer beneath the silicon substrate to enhance radiation efficiency. The fabricated transmitter array achieves an equivalent isotropically radiated power (EIRP) of 33 dBm and estimated total radiated power ( $\boldsymbol {P_{\mathrm {tot, rad}}}$ ) of 21 dBm at 264 GHz with a 3-dB bandwidth of 30 GHz while consuming 4 W of DC power and occupying a silicon area of 13 mm2. Compared to prior works at similar frequencies, the proposed transmitter array achieves a 9-dB higher EIRP than previously reported silicon-based transmitters without the use of external lens-based gain enhancement.

This paper presents a 28-GHz SiGe Doherty power amplifier (PA) that employs transformer-based matching networks and meandered coupled-line couplers to reduce chip area. Quasi-balanced and Doherty operating modes are experimentally evaluated and compared. In Doherty mode, the fabricated PA exhibits a small-signal gain of 30.1 dB. Under large-signal excitation, it achieves a saturated output power of 24.6 dBm with a peak power-added efficiency (PAE) of 31.2%. At 6-dB output back-off, the PAE remains 16.3%. With a 400-MBd 64-QAM signal, the PA delivers an average output power of 14.8 dBm and a PAE of 7.7%, at an EVM level of -25.3 dB.

This article presents two Ka-band power amplifiers (PAs) in a 130-nm silicon germanium (SiGe) BiCMOS technology achieving 31.7- (1.5 W) and 36.7-dBm (4.7 W) saturated output power while maintaining a peak power-added efficiency (PAE) of 36.7 and 28%, respectively. The PAs use a 3.5-V supply. The designs pair a refined core design method, which enables efficient device parallelization and optimized transmission line (TL) combiners. The smaller PA utilizes a single-stage 4-to-1 combiner with an expected insertion loss of 0.64 dB from electromagnetic (EM) simulation. For the larger PA, a two-stage 16-way power combiner with an insertion loss of 1.3 dB is used. Under modulated excitation with a 400-MBd 64-QAM signal, both PAs demonstrate high average output power beyond 24 and 29 dBm.

This paper presents a dual-band vector-sum phase shifter for satellite communication, implemented in 130-nm SiGe BiCMOS technology. The circuit supports 360° phase shifting in the Q- and V-band, specified as 37–43 GHz and 54–59 GHz, respectively, with a 20° phase resolution. The average measured gain after digital calibration is –2.1 dB at 40 GHz and –3.7 dB at 56 GHz. The phase shifter exhibits an amplitude RMS error below 0.5 dB and a phase RMS error below 2.5°. The circuit dissipates 57 mW of power excluding bias network and achieves an IIP3 of better than 8 dBm. The phase shifter occupies 0.073 mm2 of the IC area.

This paper presents an optimization-based behavioral model for mixers driven by multi-tone local oscillator (LO) signals, considered specifically for frequency comb orthogonal frequency-division multiplexing radar applications. Unlike traditional models, the proposed approach is designed and tested for multi-tone LO excitations. The model uses polynomial nonlinearities for both intermediate frequency and LO ports, supported by spectrum-domain fitting that selectively emphasizes strong intermodulation products. In addition, a polynomial block is introduced to capture input power-dependent phase nonlinearity. The approach is validated using circuit-level simulations and supported by measurements. Radar processing results show the model replicates distortive effects in simulations. The proposed model enables rapid system-level performance estimations and waveform optimization, replacing computationally expensive circuit-level simulations.

This paper presents a high-efficiency millimeter wave (mmW) rectifier for wireless power transfer (WPT) systems, targeting enhanced performance at lower input power levels. Leveraging a differential cross-coupled topology in 22 nm FDSOI CMOS technology, the proposed rectifier achieves a peak power conversion efficiency (PCE) of 27% at 60 GHz with 0 dBm input power and maintains a PCE above 25% across a broad input power range from -2.5 to 5 dBm. It also demonstrates wideband operation, maintaining a peak PCE above 20% from 56 GHz to 69 GHz. This performance provides greater flexibility for transmitter design and enables longer WPT distances.

This work presents compact SiGe-based RF-Integrated Circuits (RFICs) and individual building blocks for Ka-, Q- and V-band satellite communication (SatCom) payloads developed during the program ESCALAS sponsored by the German Aerospace Center (DLR). A digital interface enables Built-In Self-Tests (BIST) for autonomous calibration and in-orbit recalibration. Additionally, broadband analog predistortion (APD) linearizers are introduced. A Ka-band BIST was realized to tune third-order intermodulation products. Measurement results demonstrate excellent high-frequency performance, and radiation tolerance, confirming suitability of the presented RFICs for next-generation SatCom systems.

This work presents a broadband inverted microstrip line (IMSL) as a microwave probe for electron paramagnetic resonance (EPR) spectroscopy, a technique used to detect unpaired electron spins in biological and chemical samples. The IMSL geometry enables sample placement in the most homogeneous region of the microwave magnetic field, overcoming limitations of standard coplanar waveguide (CPW) and microstrip line (MSL) probes. Simulated and measured S-parameters confirm broadband operation up to 67 GHz. Improved field homogeneity relative to MSLs is demonstrated by a reduced coefficient of variation of the simulated magnetic field and by EPR measurements showing signal amplitudes independent of sample orientation. The IMSL geometry offers a compact microwave probe with straightforward fabrication for broadband EPR sensing in biological and healthcare applications.

We present three voltage-controlled oscillators (VCOs) with wide continuous frequency tuning range (FTR) and low phase noise (PN) for mm-wave radar applications. All three VCOs are fabricated in a 22 nm FDSOI CMOS technology and employ a common core optimized for FOM $_{T}$ using a systematic design methodology introduced in this work. VCO1 is a single-core push-push VCO achieving a FTR of $\mathbf{1 6. 7 \%}$ centered at 121.8 GHz, with a minimum measured PN of $-109.2 \text{dBc} / \text{Hz}$ at 10 MHz offset and a power consumption of only 3 mW. VCO2 is a dual-core push-push VCO employing a tail transformer (TF) that simultaneously enables tail filtering, multi-core coupling, and non-invasive second-harmonic extraction. As a result, VCO2 achieves a 3 dB improvement of mean PN compared to VCO1. Further PN reduction typically relies on ring- or star-shaped arrangements of four or more coupled cores. However, design rules of many advanced CMOS nodes prohibit arbitrary transistor rotation, limiting practical implementations to at most four cores. As a solution, VCO3 combines multiple coupling mechanisms to enable a robust octa-core $(\mathrm{N}=8)$ architecture despite these geometrical constraints. As a proof of concept, VCO3 achieves a continuous FTR of $\mathbf{1 5. 1 \%}$ centered at $\mathbf{5 2. 7 ~ G H z}$ with a minimum PN of $-125.7 \text{dBc} / \text{Hz}$, which is competitive to state-of-the-art SiGe VCOs. All three VCOs exhibit a minimum FOM $_{\text {T }}$ of $\mathbf{- 1 9 0 ~ d B c} / \mathbf{H z}$, confirming successful performance scaling from single-core to dual- and octa-core architectures. To our knowledge, this represents the best reported FOM $_{T}$ for silicon VCOs with continuous FTR at comparable frequencies.

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In broadband transmission-based electron paramagnetic resonance (EPR) spectrometers, non-resonant planar microwave probes play a key role, but very few systematic explorations of their design space exist. We develop design guidelines for two common types of transmission lines, microstrip and coplanar waveguide, to achieve a high effective microwave magnetic field strength, which ultimately leads to a more sensitive EPR measurement set-up. We compare the optimized transmission line structures and show that the coplanar waveguide achieves a higher simulated effective magnetic field strength. The simulation results are confirmed by EPR measurements up to a microwave frequency of 45GHz.

This paper presents an active W-band phase shifter based on a modified Gilbert cell with a 6-bit resolution in NXP's 140-nm SiGe:C BiCMOS technology. Several miniaturization techniques are demonstrated, including a modified transconductance stage to integrate a balun functionality without additional components. The phase shifter shows RMS amplitude and phase error of 1.3 dB and 5.4 degrees without digital calibration, respectively, and an average gain of 1.8 dB at 96 GHz. The circuit uses 37 mW of power including bias networks for phase control, from which the Gilbert cell consumes 22 mW from a 3.3 V supply voltage. The core part of the phase shifter, including balun functionality, occupies 0.026 mm(2) of the IC area.

This paper presents a V-band power amplifier (PA) designed in 22-nm FD-SOI technology, employing a transformer-based current-combining technique for emerging 5G/B5G and satellite communication applications. Operating with a low supply voltage of 0.8V, the fabricated PA delivers a gain of 21.4dB and a 3-dB bandwidth of 20.7GHz. Under large-signal conditions, the PA achieves a saturated output power exceeding 16.5dBm and a peak power-added efficiency (PAE) of over 20.9% across 42 to 58GHz. Additionally, the PA supports broadband modulation signals up to 4GBd, achieving an instantaneous data rate of 20Gb/s with 32-APSK modulation; at 50GHz, the PA demonstrates state-of-the-art performance with 12.3 dBm average output power, 9.3% drain efficiency, at an EVM level of -16.2dB.

This paper presents the design of a very compact Ka-Band power amplifier (PA) in 130 nm silicon germanium (SiGe) BiCMOS achieving an output power of 23.7 dBm and a power added efficiency (PAE) of 40% in class AB operation. A high performance is achieved through an improved approach on finding an optimized L/C-based matching network. Using this approach practical network efficiency limits can be calculated for all possible impedance transformations, enabling the assessment of network loss during the design process of power amplifiers.

In this paper the design of a fully differential Ka-Band power amplifier (PA) with transformer based impedance matching is presented. The PA is realized in a 250 nm SiGe BiCMOS process. At a target frequency of 28 GHz a maximum output power of 20.8 dBm and a PAE of 28.8 % are achieved demonstrating very high efficiency compared to implementations in similar technologies in the literature.

A broadband lumped single-ended amplifier in 0.13 mu m SiGe BiCMOS IHP technology is presented. The amplifier is designed as part of a broadband on-chip electron paramagnetic resonance spectrometer. Key parameters for this application are a small footprint and a sufficient saturated output power while maintaining a large bandwidth. The designed amplifier consists of an emitter follower and a cascode stage with series inductive peaking. The amplifier has a 3 dB-bandwidth of 60 GHz and a low frequency gain of 13 dB. The core area of the circuit occupies only 0.007 mm(2). At 30 GHz, an input referred 1dB-compression point of dBm and a saturated output power of 10 dBm is achieved.

We present the design and characterization of a power-efficient divide-by-16 frequency divider used as prescaler in a D-band radar system. The divider consists of two high-speed emitter-coupled logic (ECL) divide-by-2 stages with split-load for speed enhancement, as well as two static ECL divide-by-2 stages. All divider stages are optimized individually for low power and matched sensitivity. An analysis of the employed split-load, current-scaling, and layout optimization techniques is included in this paper. As proof of concept, the divider was fabricated in a 130-nm SiGe BiCMOS technology. Measurements demonstrate a locking range from 14-106 GHz. The divide-by-16 frequency divider achieves a self-oscillation frequency (SOF) of 86.9 GHz at a remarkably low power consumption of 90 mW including buffers. The first divide-by-2 stage dissipates only 25 mW.

This paper presents 31.7dBm and 36.7 dBm (4.7 W) Ka-band power amplifiers (PAs) in a 130nm silicon germanium (SiGe) BiCMOS technology operating from a 3.5V supply. High peak power-added efficiency (PAE) of 37% and 28% is achieved, respectively. This high output power and efficiency is enabled by refining a PA core design method for large device parallelization and optimized multi stage Wilkinson combiners. The PAs feature a single stage 4-to-1 and two stage 16-way power combiner with a simulated combining loss of only 0.64 and 1.3 dB, respectively. For a 400MBd 64-QAM signal at an EVMRMS of -25 dB, the smaller PA delivers an average output power of 24.7dBm with an average PAE of 10.6 %, while the larger version achieves 29.2dBm at 7.1 %.

This paper presents a broadband SiGe common-collector-common-base (CC-CB) two-stage linear PA with enhanced large-signal stability. Through driving-point admittance analysis, the conventional SiGe cascode PA topology, equipped with a common-emitter device, is shown to be prone to large-signal instability, rendering it unsuitable for broadband PA designs. To address this, the adoption of a CC stage is explained in detail. In addition, a stacked distributed balun is proposed for broadband output matching, accounting for the constraints of limited substrate resistivity. The proposed PA achieves a P-sat of 19.3 to 23.3dBm, with a PAE(sat) of 10.4 to 28.6% over 17 to 30GHz. The P-1dB 3-dB bandwidth ranges from 17 to 28GHz, with a PAE(1dB) of 11.0 to 22.1%. The PA supports 400-MBd 32-APSK/64-QAM signals. For 64-QAM signals, it achieves 14.7-18.9dBm/6.0-15.7% Pavg/PAE at an EVMrms level of -25dB, from 18 to 28GHz.