Modulation of the backbone rigidity via proper side chain placement and vinylene group incorporation allowed optimization of solid-state order and OFET performances.

Decision tree is one of the famous classification methods in data mining. Many researches have been proposed, which were focusing on improving the performance of decision tree. However, those algorithms are developed and run on traditional distributed systems. Obviously the latency could not be improved while processing huge data generated by ubiquitous sensing node in the era without new technology help. In order to improve data processing latency in huge data mining, in this paper, we design and implement a new parallelized decision tree algorithm on a CUDA (compute unified device architecture), which is a GPGPU solution provided by NVIDIA. In the proposed system, CPU is responsible for flow control while the GPU is responsible for computation. We have conducted many experiments to evaluate system performance of CUDT and made a comparison with traditional CPU version. The results show that CUDT is 5 ∼ 55 times faster than Weka-j48 and is 18 times speedup than SPRINT for large data set.

This paper proposes a portable three-dimensional (3D) heterogeneous system integration platform with reusable sockets, namely, morphing package Cube (MorPACK Cube). The architecture of MorPACK Cube platform achieves the features of miniaturization and portability without a carrier board. Our proposed MorPACK Cube integrates accelerometer sensor, gyroscope sensor and electronic compasses sensor and then exhibits on Andriod platform through Bluetooth wireless communication. Furthermore, we develop an Mobile APP, namely SigView, to display and analysis the collected data from these sensors. The proposed MorPACK Cube is used for sensor applications to demonstrate the effectiveness, compared with the total area 434cm2 obtained by implementing MorPACK Cube platform with a carrier board, the results show that there are 91.14% area cost reduced by the MorPACK Cube platform without a carrier board. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.

This paper proposes a heterogeneous system platform to speed up the implementation and verification of innovative design for integrating microphone array application. Comparing to state-of-the-art prototyping systems, the proposed platform named MorPACK (morphing package) achieves modularity and flexibility by adopting three concepts: substrate-level modularization, three-dimensional (3D) module stack, and components reuse. In addition, we also provide the MorPACK platform which helps designers to concentrate their efforts on their own functional module(s), and easily reuse existing modules like playing bricks, which greatly reduce the development cycle of an embedded system. The implementation results show that there are 79.13% fabrication cost reduced by the MorPACK common platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited. We adopt the microphone array cooperated with MorPACK to enhance the design flow arrangement. Furthermore, this application can be used as a reference design for distinct applications.

Recently, the key issues of Machine-to-Machine (M2M) communications also known as Machine Type Communications (MTC) are widely discussed in 3rd Generation Partnership Project (3GPP). One of the key issues for MTC is the IP addressing issue. IPv6 address space is preferred to use in MTC. However, the private IPv4 addresses are used for current configurations. Thus, the Network Address Translation (NAT) traversal problem should be resolved for MTC in 3GPP architecture. In this paper, we introduce the architectures and call flows of three NAT traversal solutions defined in 3GPP 23.888. Those are the NAT Traversal through Tunneling (NATTT) solution, the Managed NAT solution and the Non-managed NAT solution. Then we propose an Enhanced Port Forwarding (EPF) solution to minimize the impacts on the MTC device and 3GPP core network. Finally, we analyze and compare the proposed EPF solution with the existing solutions.

This paper presents a novel design flow for three-dimensional (3D) heterogeneous system prototyping platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. Based on system partition and tri-state interface connecting, the MorPACK system can be efficiently extended by system bus interfaces and can improve the functions by only updating the bare die/module. In addition, the total silicon prototyping cost of heterogeneous SoC projects can be greatly reduced by sharing the MorPACK common system platform. To demonstrate the effectiveness of the proposed platform, six SoC projects are implemented. The results show that there are 79.13% fabrication cost reduced by the MorPACK platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited.

This paper presents a boundary scan test solution for three-dimensional (3D) heterogeneous system integration platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. In order to verify the function of MorPACK platform, the interconnection wire is a critical component between circuit modules and connection modules on PCB board. The boundary scan test is used to check the correctness of interconnection wire on PCB board and then achieves high fault coverage and high quality. The simulation results show that the proposed boundary scan test solution is slightly increased in area and timing of ARM CPU with 1.4% and 1.9% respectively. The south-bridge only consumes the area plenty with 4.5%. Therefore, the proposed method can arrange the routing of PCB board to achieve the verification of interconnection wire and then obtains the small area cost without addressable scan port chip.

This paper presents an efficient memory controller VLSI design for integrating a 3D heterogeneous MorPACK system. The MorPACK system is a platform-based integration system and its structure is stacked by heterogeneous sub-modules. In order to reduce fabrication cost and increase the flexibility of memory extension, a novel multimode memory controller is proposed in this paper. The multimode memory controller supports NOR flash, NAND flash, and SDRAM memory with a wide capacity range. Hence, different MorPACK systems for various applications can be integrated by using the same multi-mode memory controller to satisfy different memory requirements. To demonstrate the effectiveness of the proposed methodology, three single-mode memory controllers are also implemented. With the technique of sharing one system-side signals, the pin count can reduce 41.9% while the pin count can reduce 19.2% by applying the technique of sharing memory-side signals. The total silicon area of single-mode memory controllers is about 6.83-mm2 in the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 3.1-mm2 of our proposed multi-mode memory controller, the results show that there are 54.7 % fabrication cost reduced.

This paper presents an investigation of analyzing various thickness of “thermal functioned” copper layers on glass-fabric-based printed circuit board (PCB). To pursue the optimum thermal solution, two strategies are proposed for improving the heat dissipation ability on PCB and reducing copper amount usage. The first one is optimizing the thermal functioned copper layer position. By analyzing different locations of copper layer, top position attains the best heat dissipation efficiency. The other one is obtaining the best cross section profile of copper thickness. Different from common uniform copper thickness, a novel various copper thickness profile model is built for heat dissipation on PCB. By monitoring chip temperature, results show that the ability of heat dissipation is advanced by proposed various thickness of the thermal-function copper layer. Comparing to uniform copper layer thickness, the proposed various copper thickness profile efficiently cools down the 0.45-W power consuming chip by 2~5 degrees with the same copper amount usage. Results show that proposed various copper thickness profile owns both benefits of higher heat dissipation ability and lower copper usage.

Due to the increasing amount of mobile devices such as smartphones and pads, the bandwidth requirements in the mobile networks are increasing exponentially. To reduce the traffic load between the smartphone and the application server on the cloud, we propose a context-aware mechanism where the smartphones and the network nodes report their contexts to the application server. The application server selects suitable video stream to deliver in order to reduce the bandwidth requirement and maintain good display quality.

This paper proposes a modularized three-dimensional (3D) heterogeneous system integration platform architecture, namely, MorPACK (morphing package). The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. An efficient reconfiguration is enabled thanks to the use of system bus interfaces and exchange the bare die/module by system dividing and tri-state interface connecting. Six SoC projects/designs are implemented to demonstrate the effectiveness of the proposed MorPACK platform. The average silicon area of each project is about 122.59 mm2 using the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 587.44 mm2 obtained by implementing these projects separately, the results show that there are 79.13% fabrication cost reduced by the MorPACK platform. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.

Classification is an important issue both in Machine Learning and Data Mining. Decision tree is one of the famous classification models. In the reality case, the dimension of data is high and the data size is huge. Building a decision in large data base cost much time in computation. It is a computationally expensive problem. GPU is a special design processor of graphic. The highly parallel features of graphic processing made today’s GPU architecture. GPGPU means use GPU to solve non-graphic problems which need amounts of computation power. Since the high performance and capacity/price ratio, many researches use GPU to process lots computation. Compute Unified Device Architecture (CUDA) is a GPGPU solution provided by NVIDIA. This paper provides a new parallel decision tree algorithm base on CUDA. The algorithm parallel computes building phase of decision tree. In our system, CPU is responsible for flow control and GPU is responsible for computation. We compare our system to the Weka-j48 algorithm. The result shows out system is 6~5x times faster than Weka-j48. Compare with SPRINT on large data set, our CUDT has about 18 times speedup. 關鍵詞:GPGPU、CUDA、Decision Tree、Classification

This paper presents a thermal analysis result for a 3D heterogeneous embedded system integration MorPACK (morphing package) platform. The MorPACK platform is stacked by heterogeneous submodules composed of bare dies, a substrate, connection bridges, and solder balls. Since the tiny, heterogeneous and integrable characteristics of MorPACK platform, it needs to be fabricated in high-density and laminar structure. The cooling ability of forced convection is restricted. This study presents an important characteristic for this 3D structure and two indications to optimize thermal solution for MorPACK structure. The characteristic shows the lowest layer owns the best cooling condition, so the bare die chip with highest power consumption should be placed on the lowest layer. It achieves cooling a 0.45-W consuming chip by 12-degree more than it put on the top layer. One of the indications shows the vertical thermal conductivity can be improved by filling up whole MorPACK with mold material. This skill efficiently cools down the 0.45-W consuming chip by 10-degree more than non-filled-up structure. The other indication shows removing the connection bridges and cutting out the substrate to make a room space for chip placement. With result shown, 50 % height and volume of MorPACK can be minimized and also reduce thermal resistance in out-plan direction.

Classification is an important issue both in Machine Learning and Data Mining. Decision tree is one of the famous classification models. In the reality case, the dimension of data is high and the data size is huge. Building a decision in large data base cost much time in computation. It is a computationally expensive problem. GPU is a special design processor of graphic. The highly parallel features of graphic processing made today's GPU architecture. GPGPU means use GPU to solve non-graphic problems which need amounts of computation power. Since the high performance and capacity/price ratio, many researches use GPU to process lots computation. Compute Unified Device Architecture (CUDA) is a GPGPU solution provided by NVIDIA. This paper provides a new parallel decision tree algorithm base on CUDA. The algorithm parallel computes building phase of decision tree.

There are many studies that have been conducted about the integrated use of statistical process control (SPC) and engineering process control (EPC) because using them individually cannot optimally control the manufacturing process. The majority of these studies have reported that the integrated approach has better performance than using only SPC or EPC. Among all these studies, most of them have assumed that the assignable causes of process disturbance can be effectively identified and removed by SPC techniques. However, these techniques are typically time-consuming and thus make the search hard to implement in practice. The paper discusses the development of neural network models with independent component analysis (ICA) to identify the disturbance and recognize shifts in the correlated process parameters. Moreover, these designed network models can be used to monitor and eliminate manufacturing process parameters when disturbance happens in the underlying process. For comparison, the traditional Shewhart chart and cumulative sum (CUSUM) chart, were constructed for the simulated data sets to evaluate the identifying capability of the proposed approach. As the results reveal, the proposed approach outperforms the other methods and the shift of disturbance can be identified successfully.

The aim of this study was to evaluate the effect of the consumption of purple sweet potato leaves (PSPLs) on the immune response and the modulation of that response in 15 basketball players during a training period. They completed the 7-week study consisted of a run-in period (week 1), a PSPLs diet (200 g PSPLs/d; weeks 2, 3), a washout period (weeks 4, 5), and a control diet (low polyphenols content and carotenoid content adjusted to the same level as that of PSPLs diet; weeks 6 and 7). Blood, urine, and saliva samples were collected for biochemical analysis. The results showed that the plasma polyphenols concentration increased significantly in the PSPLs period. Compared with the control period, the PSPLs consumption produced a significant increase in the proliferation responsiveness of peripheral blood mononuclear cells (PBMC), cytotoxic activity of nature killer (NK) cells, and secretion of interferon (IFN)-gamma. However, no significant increase in the secretion of salivary immunoglobulin A (sIgA), interleukin (IL)-2, or interleukin-4 was observed after PSPLs consumption. In conclusion, consumption of a PSPLs diet for 2 weeks can modulate the immune response of basketball players during a training period.

The aim of this study was to evaluate the effect of purple sweet potato leaves (PSPLs) consumption on antioxidative status and its modulation of that status in basketball players during training period. Fifteen elite basketball players were enrolled in this study. The seven-week study consisted of a run-in (week 1), PSPLs diet (daily consumption of 200 g PSPLs) (weeks 2, 3), washout (weeks 4, 5), and control diet (low polyphenol, with the amount of carotenoids adjusted to the same level as that of PSPLs) (weeks 6, 7). Blood and urine samples were taken for biochemical analysis. Compared with the control group, the results showed that PSPLs consumption led to a significant increase of plasma polyphenol concentration and vitamin E and C levels. Low density lipoprotein (LDL) lag time was significantly longer in the PSPLs group. A significant decrease of urinary 8-hydroxy-2-deoxyguanosine (8-OHdG) was noted; however, there was no significant change in plasma glutathione (GSH), total antioxidant status (TAS) and malondialdehyde + 4-hydroxy-2(E)-nonenal level after consuming the PSPLs diet. In conclusion, consumption of PSPLs diet for 2 weeks may reduce lipid and DNA oxidation that can modulate the antioxidative status of basketball players during training period.

Credit scoring has become a very important task as the credit industry has been experiencing double-digit growth rate during the past few decades. The artificial neural network is becoming a very popular alternative in credit scoring models due to its associated memory characteristic and generalization capability. However, the decision of network's topology, importance of potential input variables and the long training process has often long been criticized and hence limited its application in handling credit scoring problems. The objective of the proposed study is to explore the performance of credit scoring by integrating the backpropagation neural networks with traditional discriminant analysis approach. To demonstrate the inclusion of the credit scoring result from discriminant analysis would simplify the network structure and improve the credit scoring accuracy of the designed neural network model, credit scoring tasks are performed on one bank credit card data set. As the results reveal, the proposed hybrid approach converges much faster than the conventional neural networks model. Moreover, the credit scoring accuracies increase in terms of the proposed methodology and outperform traditional discriminant analysis and logistic regression approaches.