3D heterogeneous chip integration is suggested to overcome 2D conventional package limitation. CoW (Chip on Wafer) with TSV (Trough silicon via) is the essential technology for various advanced package platforms such as 2.5D, 3D, and System in package (SiP). In this study, thermal compression bonding (TC-Bonding) with pre-applied underfill material was used for wafer level chip assembly. Optimum underfill volume and fluid behavior during TC-Bonding was engineered successfully based on fluid dynamic simulation and self-designed mathematical equation. According to these studies, fine bump pitch assembly was accomplished by solder sweep suppression. Underfill material coverage was also improved to minimize keep out zone (KOZ) for 3D IC bump pattern design flexibility. Moreover, fillet size was minimized to 4.2% of top chip area and the assembly yield over 97% was achieved. In study, 3D CoW process over 100k bump counts with 25um bump pitch was successfully demonstrated and TC bonding process window was secured even without experimental result.

Advanced packaging continues to attract a lot of attention as the demands for higher performance, higher bandwidth, and lower power consumption increase. To satisfy aforementioned demands, researchers have tuned to 3D IC technology such as X-Cube using micro-bumps announced by Samsung in 2020. As much higher I/O bandwidth with smaller form factor is required, hybrid Cu bonding (HCB) is considered as one of the most promising technologies for the next-generation 3D-based chip products. Unlike the conventional solder based chip bonding, HCB can achieve fine pitch bonding by connecting copper-to-copper and oxide-to-oxide directly. HCB technology enables sub 10 um bonding pitch as well as improves electrical performance with no power and signal penalty. However, there are many challenges affecting HCB interface quality. Detailed understanding and analyses are necessary to obtain reliable fine pitch interconnects. In this paper, key factors, which impact the electrical connectivity and reliability of HCB, are investigated using die-to-wafer HCB chip with 4-μm pitch and 2-μm pad. The dishing and bonding accuracy are analyzed and precisely controlled to achieve robust electrical connection. As an effort to achieve void free interconnects, the characteristics of voids according to the type and size of particles are analyzed quantitatively. The electrical connectivity and reliability were demonstrated through the investigations of key factors of HCB. It was verified over 98% electrical connectivity for all 210 chains on the chip. All the chips both large top and small top structures, that were assigned to each category of reliability tests, including TC, u-HAST, and HTS, passed the package level reliability tests.

There has been lots of requirement to increase the I/O bandwidth and thermal characteristic in flip chip base package. Next-generation 3D SiP products need a gapless hybrid Cu bonding (HCB) process to overcome extremely small bonding pitch and distribute the heats from bottom die. Unlike conventional solder base chip bonding, there are various void sources in gapless HCB process, such as small particles and surface topology, where the interface between the bottom wafer and top chip is in contact without a bonding medium. In addition, the bonding voids have critical risk such as Si popping in the subsequent heat treatment process. Therefore, the control of bonding void in the development of the HCB process is very important for mass production. In this paper, the cause of the occurrence of bonding void is identified and several management factors are proposed in terms of design, process and operation.

Hybrid bonding technology is required for high density I/O in the 3D package structure to overcome the limitations of thermos compression bonding. Compared to bump bonding with micro solder, hybrid bonding can achieve fine pitch bonding and have excellent SI/PI characteristics. One of the key technologies of hybrid bonding is pad processing which is optimized for the bonding environment. We should consider Cu expansion at anneal temperature and bonding area between pads because the expansion of Cu pad is proportional to temperature and pad volume. [1]However, annealing temperature is determined depending on the thermal properties of the device. Hence, it is important to adjust pad dishing so that connectivity can be secured at annealing temperature. The initial pad design including pad dishing should be determined by expecting thermal expansion at process condition. The amount of Cu extrusion at annealing can be adjusted with an appropriate pad size, or by changing bonding shape. Therefore, design rule for fine pad pitch is required based on the relationship between Cu pad surface area and height.In this study, we evaluate various factors of layout for fine pitch hybrid bonding. Bonding quality was investigated according to the surface topology and misalignment of bonding pad. The effect of bonding area was studied by using misalignment via chain that changed up to 0-95%. Through the experiment, we can define specific design rule showing high yield for fine pitch hybrid bonding.

Logic device for AI-inference needs high band width and low latency characteristics to increase the response speed. In order to overcome the size limitation of a single logic chip and secure these characteristics, it is inevitable to separate the SRAM function to increase the memory capacity and apply a 3D package structure that directly stacks with logic. The structure of stacking logic and memory can be implemented in four cases; face to face and back to face (B2F), Logic on SRAM and SRAM on Logic. Among them, thermal characteristics in SRAM on Logic with B2F are not stronger than other structures because in a server environment where most of the heat is forcibly discharged through the cooler installed on the top of package, a lot of heat generated from the logic front side does not go directly to the cooler through Si alone, but passes through the micro-bump bonding layer and the entire SRAM chip. In this study, it was presented that a detailed method for reducing the thermal resistance of the micro-bump junction in order to improve the thermal characteristics in the SRAM on Logic stack package structure. Test vehicle consisted of top chip (93mm 2 ) and bottom chip (103mm 2 ) with micro-bump connections of under $40 \mu\mathrm{m}$ in pitch and under $20 \mu\mathrm{m}$ in diameter. The main influence factors were analyzed in terms of the joint structure, material, and layout design, and thermal resistance was measured and compared after achieving actual package to confirm exactly the effect of each major factor on reducing package thermal resistance.