Hybrid bonding is being evaluated for advanced packaging of 2.5 and 3D modules due to the enhanced scalability and performance (thermal, electrical and reliability) of the interconnect. The direct bond interconnect (DBI®) Ultra technology is a die to wafer hybrid bonding assembly process that uses all die handling on dicing tape frames. We explore the assembly of various die sizes, pad and pitch dimensions to identify fundamental challenges and solutions to accelerate adoption of this technology in manufacturing. In this paper, we discuss the assembly process results of a test vehicle with an interconnect design of 3.5 μm pad on 7 μm pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 1,400 to 520,000 links. The component wafers were diced and transferred to tape frame for subsequent die preparation for bonding. The 3.5 μm bond pad requires sub-micron alignment accuracy within the bonder for 100% alignment yield. However, with careful process control, alignment yield greater than 98% and void free yield of 96-99% was achieved using a bonder with 3 μm alignment accuracy. The die stacks were characterized with electrical resistance measurement, C-mode scanning acoustic microscopy (CSAM), and cross-section microscopy analysis. A process to evaluate the defectivity in daisy chain test vehicles is described that includes correlation of alignment accuracy, CSAM and daisy chain electrical resistance. These test vehicles are compared to previous studies with pad sizes of 2 –10 μm.
The growth in demand for small form-factor and more capable electronic devices is driving a corresponding need for for advances in high-density interconnect technology to support high-speed, power efficient data transfer between chiplets or between systems-on-chip and memory. This paper presents, for the first time, electrical modeling and characterization results for $2-\mu \mathrm{m}$ line and space (L/S) and $1.5-\mu \mathrm{m}$ L/S signal wiring in high-density wiring layers in a panel-level organic interposer to address this need. The first part of this paper shows various high-density routing configurations $(< 5\mu\ \mathrm{m})$ formed in organic thin films, explicitly focusing on the effect on signal phase delays, crosstalk, insertion loss, and the range of characteristic impedance that fine line structures can provide; in this discussion, impedance matching to mitigate reflections is considered. To verify high-density signaling models, the second part of the paper focuses on electromagnetic simulations and hardware measurements taken at frequencies up to 20 GHz for 5.9-mm and 1.3-mm single-ended transmission lines. In addition to the agreement between measurement and simulation results for both $2-\mu \mathrm{m}$ and $1.5-\mu \mathrm{m}$ L/S configurations up to 20 GHz, this paper quantifies measured per-unit-length insertion loss of the high density wires at multiple frequencies to serve as a standard of comparison.
With the popularization of wide band-gap power modules in offshore wind power systems and water surface photovoltaic power stations, packaging materials face challenges of corrosion by salt, blended with high humidity. Copper-silver (Cu-Ag) composite sintered paste was proposed by researchers as a novel die-attach material for a lower cost and anti-electro migration ability. However, the potential difference between copper and silver forms galvanic corrosion in a high-humidity environment, resulting in accelerated failure combined with salt mist. To further promote the application of composite sintered materials, a copper-silver double-sphere galvanic corrosion model based on finite element simulation was proposed in this paper. The relationship between corrosion rate and time of different Cu-Ag particle size combinations under different sintering degrees was predicted by initial exchange current density. Through the electrochemical characterization of the sintered samples, the optimal combination of materials was further discussed. The accuracy of the model was also verified. The conclusions obtained from both the experiments and simulation work provide guidance for future anti-corrosion analysis, as well as the reliability improvement of novel composite sintered materials.
Transient-liquid-phase (TLP) Cu-Sn bonding is an attractive method for fabrication of intra-chip connects in 3-D and chiplet applications due to the ease of manufacturing and low cost. With the continuous increase in the interconnect densities, it is highly desired to shrink the Cu-Sn bump diameters to $\mathbf{5}\ \boldsymbol{\mu} \mathbf{m}$ or less from the current mainstream $\mathbf{20}\sim \mathbf{30}\ \boldsymbol{\mu} \mathbf{m}$ . However, small Cu-Sn bumps shows significant difference from large ones because some surface related properties that are insignificant for large bumps become dominant for small ones. This paper reports the differences between bonding of large and small Cu-Sn bumps, such as surface oxidation and bump undercut, and proposes the methods to address these problems. By optimizing the bonding processes, TLP bonding of Cu-Sn bumps with a $\mathbf{5}\ \boldsymbol{\mu} \mathbf{m}$ diameter has been successfully achieved.
The demand for higher thermal performance package increases and this is exacerbated by the increased of die and packages sizes. The insufficient coverage, interfacial separations, voids, and thicker Bond Line Thickness (BLT) of Thermal Interface Material (TIM1) caused by package materials and assembly processes prevent good thermal performance. Thermal impedance better than 15 mm2-C/W is needed for high-power applications. Lower thermal impedance is better for thermal performance. This work evaluated next generation TIM1s with thermal conductivity ranging from 4 to 10 W/m-K, the assembly of these materials with different lid attach processes and their reliability. It allowed Marvell and its OSATs to select the TIM1 that meets the thermal requirement of large die & package.
The long-term reliability of the interconnection in crystalline silicon solar cell photovoltaic (PV) modules is crucial for ensuring optimal performance for up to 25 years. Most failures in crystalline silicon PV modules are caused by breakage of the solder joint interconnection during daily thermal cycles. The conventional interconnection technologies use low-melting-point materials such as lead or lead-free solder, which lack sufficient heat resistance. As a result, improved interconnection technologies are needed. Nickel micro-plating bonding (NMPB) is a new technology that replaces lead or lead-free solder bonding with copper wires bonded with Ni electroplating film. To evaluate the lifespan of NMPB interconnected PV module, modules were fabricated by using both NMPB and solder bonding with EVA and further encapsulants. Thermal cycling (TC) tests were performed, and the results showed that the retention rate of the maximum output power (P-max) of NMPB interconnected PV module was 12.8% higher than that of solder bonding module after TC cycles.
Healthcare with continuous bio-signal monitoring is one of the leading applications of wearable technology. More and more functions, such as Electrocardiography(ECG) and blood chemicals, are to trigger next waves of blooming demand in the wearable device market. We introduced world's first ECG biosensor in ear-tip in 2022 ECTC conference [1] by using conductive liquid silicone rubber (LSR) as molding material to form 3D flexible SiP structure as well as ECG sensor electrode. Conductive LSR(CLSR) is a promising material for such a purpose. However, ways to improve adhesion among heterogeneous parts and the reliability to the level of wearable usage are critical. In this paper, material properties of the LSR are explored, and it is found that the silicon based primer, when applied to the interface properly, can be a way to greatly improve adhesion between conductive LSR and several other materials commonly used in the system-in-package integration. In order to quantify the adhesion between silicone elastomers and other parts, ASTM D3330 pull-off test is proposed, performed, and result shown in this paper. In combination with reliability test, very positive results are obtained by using the primer for wearable user scenario. The insights to the material properties are keys to the selection and use of the primer. It is concluded the conductive LSR(CLSR) meet these needs of heterogeneous integration of SiP for bio-sensing applications of wearable devices
The growing need for wearable devices has increased the interest in thin, flexible power sources. A fundamental understanding of the degradation of power sources in consumer electronics devices is required to determine survivability over the useful life and inform the user of the battery's state-of-health health and remaining useful life in real-time. Battery testing in prior work often involves accelerated life cycling with fixed charge-discharge limits and fixed charge and discharge currents (C-rates) per cycle. Fixed conditions testing does not represent the real-world use case scenarios of products with random end-ofcycling limits. Furthermore, the models developed using fixed cycling data are often tested on datasets with the same characteristics as the training data, i.e., fixed depth of cycling and C-rates. The model accuracy in such cases can often be misleading as the model is not tested on randomized cycling/charging datasets, which are the norm in real-world use-case scenarios. To this end, the current work focuses on accelerated life cycling tests of batteries with random variations in charge-discharge depth and C-rates, individually and simultaneously. Multiple iterations of the SOH estimation models have been presented with different predictor variables to minimize the model validation error. Four different SOC-bound limits were chosen for the randomized depth of cycling of the battery samples, and the C-rate was varied between 0.5C-2.5C. In addition, four different model variants were chosen considering the voltage profile of the battery using charging and discharging. All the model variants estimated the random depth of cycling SOH with high accuracy, the most common type of battery use-case scenario occurring in the real world. All the model variants estimated the random C-rate, combined randomized depth of cycling, and randomized C-rate SOH with intermediate accuracy.
In this paper, we first design an antenna array with dual linear polarizations, then a four-layer transmitarray to convert linear polarizations to circular polarizations, which operates in the Ku-band downlink satellite band (10.7 GHz~12.75 GHz, center frequency at 11.7 GHz). Bisected Split- Ring structure was employed in the transmitarray design due to its larger bandwidth in circular polarization axis ratio and lower insertion loss properties. The unit cell of FSS is 0.46 $\lambda\times$ 0.46 $\lambda$ , and the incident wave must be incident at $45^{\circ}$ (the angle between E-field of the incident wave and the y-direction) to convert linear polarization to circular polarization. The phase control is approximately 130° in range, the oblique incidence range is approximately 0-20°, and the transmitarray diameter was 124 mm. The measured gain of the dual-polarized antenna array with the transmitarray was about 18.8 dB and 18.6 dB, with the y-polarization waves turning into left-handed circular polarization (LHCP) and the x-polarization waves to right- handed circular polarization (RHCP). The measured 3 dB axis ratio BW ranges from 11.66 to 11.97 GHz. Then we rotated further the original design of the transmitarray by $45^{\circ}$ in z-axis. The dual-polarized array antenna will maintain the original polarization direction through the transmitarray. The measured gain of the transmitarrav prototype is 20.16 dB and 20.16 dB. Our experimental measurements match well with the simulated. With dual illuminations, all four polarizations (V-LP, H-LP, LHCP, and RHCP) can be obtained by simply turning the FSS by $\pm 45^{\circ}$ .
The growing reliability risk of board-level solder joints for large body size semiconductor devices requires the evaluation of new countermeasures at multiple stages of the component and system development process. For high power devices, the challenge is further elevated due to the interaction with thermal solution hardware. In this study, a Reliability Improvement Measure (RIM) is deployed at the assembly level, and its performance is compared with a design that does not incorporate this measure. Assemblies with and without RIM are evaluated using temperature cycling, and the characteristic life and solder microstructure are analyzed at the conclusion of the test. Numerical simulations are adopted to provide insight into performance differences. For both configurations, corner solder joints experience the highest level of stress and accumulation of damage. However, the adoption of RIM reduces the level of stress significantly, thereby decreasing fatigue and extending the life of the solder joints. At the microstructure level, recrystallized grains are observed at the component side of the solder joints for both configurations. However, the extent of recrystallization and cracking are more pronounced in the units without RIM. The results from this work highlight the importance of conducting early reliability assessment and demonstrate that product level reliability can be effectively managed with the appropriate solutions.
We report an efficient approach to integrate semiconductor laser array with photonic integrated circuits (PIC) in an optical transceiver architecture aiming for 1.6 Tbps. Key features including waveguide alignment layer, multi-tip edge coupler, pedestals, alignment marks, and under-bump metallization are used to achieve efficient integration and optical coupling.
Hybrid bonding or surface activated bonding is becoming the technology to manufacture higher density first-level interconnects by addressing pitch scaling difficulties of solder interconnects. One of the major challenges for dielectric bonding is to decrease the process temperature to be compatible with stacking schemes and device limitations. In this paper, we focus on both low temperature SiCN dielectric deposition and low temperature annealing temperatures (<250°C). Both physical vapor deposition (PVD) and plasma enhanced chemical vapor deposition (PECVD) of SiCN are investigated side by side. Films of various densities and stoichiometries are compared; pre and post activation hydrophilicity, post activation dangling bond densities are characterized to explain how to tune SiCN films for improved bond energy at low annealing temperatures.
We present a demo system of FPGA-driven time-delay photonic reservoir computer. The architecture of the reservoir is based on a high bandwidth density optical interconnect technologies using VCSEL and photodiode chips with multi-mode optical fiber, and specially designed polymer waveguides. Using the demo system, we also present the results on voice utterance dataset. This reservoir is promising for a power-efficient board-integrated photonic neural network.
Nowadays, high-end electric devices such as high-performance servers and computers have been attracting attentions so as to accelerate social implementation of high-speed networking systems. In those devices, especially for 2.xD semiconductor packages with HBM2 and logic dies, interposers play a key role for realizing high-density, high-speed and high-reliable connections between those dies. So far, wide varieties of interposer structures have been proposed in fabrication platforms. We demonstrated two categories of interposer assembly in large panel size. RDL-interposer having multi-layered Cu wirings and die embedded interposer were fabricated in large panel size applicable to so-called 2.xD semiconductor package. We also demonstrated fabrication of fine Cu wirings covered with inorganic protection layer for stable electrical reliability.
We propose a comprehensive investigation of solder joint reliability that compares eutectic SnBi BGA interconnections to novel hypoeutectic Sn-Bi interconnections formed using commercially viable Solid Liquid Inter-Diffusion (SLID) conditions that enable low temperature reflow at both the package and card levels. The homogeneous and stable hypoeutectic SnBi connections, comprising a lower Bi content than their eutectic counterparts, demonstrate favorable resultant properties. A double SLID method and its diffusion kinetics are examined by employing various mask sizes to ensure that the required volume of eutectic SnBi solder paste for complete homogenization can be supplied in a packaging and card attach production environment. Combinations of fully homogeneous and near homogeneous interconnections are reported, with unreacted SAC being less than 10% by volume and Bi% in homogeneous interconnections ranging from 28 to 32%. Secondly, because of reported issues with ENIG metallization, interconnections with Cu metallization pads are investigated. These homogeneous hypoeutectic SnBi interconnections are evaluated for reliability performance with comparison to eutectic Sn58Bi interconnections. Specifically, three stress tests are used - high temperature storage (HTS), high temperature storage with bias (HTSB) and accelerated thermal cycling (ATC). Progressive electrical and mechanical responses are explained through observations of microstructural evolution (grain size, intermetallic formation, etc.). The results show that hypoeutectic SnBi and eutectic SnBi interconnections remain relatively stable through Telcordia stress conditions with minor degradations observed only in the eutectic case. However, the newly formed hypoeutectic SnBi interconnections exhibit notably superior reliability performance over their eutectic SnBi counterparts under extended JEDEC conditions thus far, recommending their use in such applications.
In this study, the heterogeneous integration of three chips including an FPGA, HBM, and IBM AI chip on an organic interposer substrate using Cu-pillar micro-bump solder joint is investigated. The largest chip is the FPGA with a size of approximately 29 mm x 12 mm and containing more than 188,000 pads at 40 um pitch. The organic substrate used in this study is 55 mm x 55 mm square with 4+1 7-2-7 layers and ENEPIG (electroless Ni/Pd/Au) surface finished pads. 2 um/2 um line and space RDL was used on the build-up substrate to achieve high-bandwidth interconnection between the FPGA and HBM. Belt-furnace reflow and normal thermo-compression bonding (TCB) processes could not connect the fine-pitch micro-bumps of large FPGA die without non-wet or solder bridging defects due to warpage and CTE differences. Therefore, to solve these issues, we have developed a new solder deposition technique that uses IMS (injection molded solder) to form a specified volume of solder in the right place on the organic interposer substrate. This advanced IMS process varied the solder amount across the die site to decrease volume in areas prone to bridging and increase volume in areas prone to non-wetting. The underfill process was also optimized to reenforce the package and reduce the stress from the substrate warpage and CTE mismatch. Selective cross-sectional analysis was used to study the geometry of micro-bumps after the chip join, and confirmed the micro-bumps were joined without defects. The results of the electrical measurement test after assembly confirmed that no short circuit has occurred.
Current limitations of silver sintering are long processing times and high processing temperatures. To overcome these restrictions, different tin contents are added to the sintering paste. Various preheating times and processing times are evaluated at a processing temperature of 235°C. The positive effect of micro scale tin particles on shear strength and porosity at reduced process parameters is demonstrated. The addition of tin particles enables a reduction of both the processing temperature and time while maintaining high shear strengths. At a processing time of 60 s and no preheating time, the addition of 27.5 at% tin to the sintering paste leads to an increase in shear strength of 417 % from 4.6 MPa to 19.2 MPa, compared to the sintering paste without an alloying element. Energy-dispersive X-ray spectroscopy shows the homogeneous distribution of the alloying element in the joint that has been fabricated with the produced sintering paste. The porosity of the sintered layer is reduced by the addition of tin as alloying element which can improve the electrical and thermal properties as well.
