Accurate device modeling, short-circuit prediction, and protection for silicon carbide (SiC) mosfets require accurate measurement of their saturation characteristics under high drain-source voltages. However, conventional curve tracers are limited by power constraints, parasitic elements, and especially the device's intrinsic turn-on time, which together constrain di/dt. This makes it difficult to characterize behavior in high-voltage, high-current regions, since the long duration required to reach steady state can cause significant self-heating, reducing accuracy or even damaging the device. This letter proposes a test topology using multiple parallel devices as auxiliary switches to control the measurement and accelerate the turn-on transient while keeping the device under test normally on. To accurately measure the internal gate voltage during an ultra-narrow pulse, we propose a high-impedance gate drive circuit, eliminating the influence of the voltage drop across the device's intrinsic gate resistance. The measured results capture the full range of transfer and output characteristics of the SiC mosfet and show good agreement with curve tracer data in the low-voltage region. At V-ds = 20V and V-gs = 20V under room temperature, the proposed method limits the temperature rise to within 4 degrees C, compared to nearly 100 degrees C with a power device analyzer, thereby enabling more accurate device characterization and modeling.

Series connection of SiC MOSFETs is an effective method to increase the blocking voltage of power devices. However, research on voltage-sharing behavior and protection under short-circuit (SC) conditions remains limited. Due to the poor SC robustness of SiC MOSFETs, improving voltage balance during SC events is critical for reliable series operation. This work characterizes the temperature dependence of the saturation current using ultra-short pulse testing on a single device. By modeling the gate-source voltage (Vgs) dependence of the saturation current, the proposed method reveals the physical mechanism behind SC voltage imbalance and provides a general guideline for its mitigation. Experimental validation confirms the analysis, and comparative tests demonstrate how adjusting Vgs expands the positive temperature coefficient region, improving dynamic voltage balance. The proposed model offers practical guidance for device selection and SC protection design in series-connected SiC MOSFET applications.

Silicon carbide (SiC) MOSFETs have been widely adopted in power electronics applications. However, their robustness, particularly short-circuit robustness—remains a critical limitation. This work investigates the short-circuit characteristics of two SiC MOSFETs with planar-gate and trench-gate structures. Experimental results showed that both devices exhibited gate-voltage drop during short-circuit events, with a more pronounced voltage drop (3.8 V) observed in the planar-gate device. During the turn-off phase, the planar-gate MOSFET also showed a larger drain current tail compared to its trench-gate counterpart. In addition, both devices experienced delayed gate failure after short-circuit operation. By employing calibrated TCAD simulations, the influence of Fowler–Nordheim (FN) tunneling current and hot-carrier injection current on the gate-voltage drop was analyzed. The theoretical relationship between the drain current tail, the junction temperature and the applied voltage was derived, which explained the observed difference between the two device structures. Finally, thermomechanical stress analysis during the short circuit operation revealed the evolution of aluminum layer and the fracture mechanism of the interlayer dielectric (ILD) above the gate. These phenomena led to the formation of conductive paths, which were identified as the root cause of delayed gate failure. Analysis of failed devices using OBIRCH (Optical Beam Induced Resistance Change), FIB (Focused ion beam), and EDS (Energy-dispersive X-ray spectroscopy) confirmed the presence of melted aluminum and conductive channels within the ILD, validating the failure mechanism.

Implementation of large virtual inertia with high stability margin is a significant challenge for DC microgrid systems. In this paper, a filter time constant, a new degree of freedom, is utilized to enhance voltage loop stability and its relationship with virtual inertia and stability margin is further explored. Then, the virtual resistance concept is introduced as an intuitive design parameter to decouple stability margin from virtual inertia. In this way, large virtual inertia can be realized in a simple and practical way, making it easy to be emulated quantitatively and applied in engineering practice. Moreover, performance analysis of virtual resistance is conducted, which suggests virtual resistance with proper value brings little effect on its dynamic response while greatly enhances stability margin. Finally, the proposed decoupling method is validated in both simulation and experiment.

BackgroundRadioresistance is a major problem in clinical treatment of nasopharyngeal carcinoma (NPC), and molecular mechanisms of radioresistance related to the antioxidant system are unknown. TXNIP (thioredoxin-interacting protein) is an endogenous inhibitor of thioredoxin. The system xCT/GSH/GPX4 axis is an important antioxidant system of ferroptosis in drug-resistant solid tumor therapy. It is of great clinical significance to study TXNIP and ferroptosis in the role of NPC radioresistance for the therapeutic effect of NPC patients.MethodsImmunohistochemistry, qRT-PCR, and WB were used to analyze the expression of TXNIP in clinical samples and NPC cells. Clone formation detected the radioresistance of cells. Flow cytometry, immunofluorescence, and WB were used to analyze intracellular ROS levels and the expression of GPX4 and xCT. Related kits were used to analyze Fe2+, MDA, GSH, and mitochondrial membrane potential. A nude mice subcutaneous tumor formation experiment was used for further verification.ResultsTXNIP was less expressed in the NPC radioresistant group than in the radiosensitive group. Overexpression of TXNIP promoted apoptosis of NPC cells and showed a dose-dependent response to radiation. In addition, with radiation, TXNIP increased intracellular ROS levels, decreased the expression of GPX4 and xCT, affected the production of intracellular metabolites, such as Fe2+, MDA, and GSH, and induced ferroptosis in cells. Stabilized overexpression/knockdown cells significantly affected the growth of tumors in nude mice with radiation.ConclusionsTXNIP is a radiosensitive and ferroptosis-associated gene, which can reverse the radioresistance of NPC by promoting ferroptosis in a dose-dependent manner and through the xCT-GSH-GPX4-ROS axis.

DC-DC solid-state transformer (SST) is becoming more and more popular for medium voltage applications. This topology, due to its modularity, has the potential to present high levels of reliability. However, there is a lack of a proper design method that ensures reliable converter operation with minimal total cost of ownership. In this paper, a reliability model of the DC-DC stage of the SST is presented that includes infant mortality, random failures, and aging failures while considering and comparing the 2-level full-bridge and the 3-level half-bridge as possible submodule configurations, which are conventional solutions in SST systems. Furthermore, an analytical expression on the total cost of ownership of the converter is developed which includes installation, operation, repair, and downtime costs. A minimization problem is then formed with objective function the total cost of ownership and the number of redundant submodules as degrees of freedom. A case study is given to demonstrate the analysis and conclusions that can be drawn using the proposed method. The analysis shows that despite the increase in initial investment costs, redundancy can lead to significant reductions in total cost of ownership over the lifetime of the converter. In addition, design decisions can be severely impacted by the cost of downtime and the ability to restore the operation of the converter quickly after a fault.

The medium-voltage grid emulator is gaining popularity for testing grid-code compliance of large-capacity converters for renewable energy resources. The cascaded H-bridge converter based on active-front-ends is a promising candidate for high-power grid emulators owing to its high modularity and extendibility. However, the cascaded H-bridge topology-based grid emulator suffers the undesired and unpredictable large dc-link voltage ripple under output voltages with multiple-frequency components, e.g., when emulating the grid voltage flickers and harmonics. In this article, the dc-link voltage ripple characteristics under multi-frequency output conditions are analyzed and a dc-link ripple suppression method adopting harmonic current injection is proposed. The injected current reference is generated by reconstructing the dc-link output current and added to the original active-front-end current control loop. Compared with the existing control methods, e.g., proportional-integral-resonant (PIR), the proposed method has a good voltage ripple suppression effect, especially for multi-frequency outputs. Furthermore, the proposed idea does not need complicated calculation or extra control loops and provides a feedforward reference for the current control, leading to a good dynamic response of dc-link voltage control. Finally, the performance of this suppression control scheme is verified on two 1200 V@40 kW power electronics building blocks of a cascaded H-bridge converter.

Medium voltage (MV) dual active bridge (DAB) converter with series-connected SiC MOSFETs (S-SiC) is a promising solution for high power density isolated DC/DC converter. To improve the voltage sharing and reliability of S-SiC, relatively large snubber capacitors are connected in parallel with S-SiC. But this narrows the zero voltage switching-on (ZVS-on) range of S-SiC, and even reduces the efficiency and reliability of the entire converter. Adding non-optimized internal phase shift angle to the low-voltage (LV) side switching unit will result in excessive circulating power and still lead to low efficiency. In this paper, the phase-shift angle segmentation modulation (PSSM) scheme featuring soft-switching performance is proposed for a MV DAB converter with S-SiC. The proposed modulation scheme is based on a detailed derivation of the ZVS-on range and operation modes. Then, the changes in operation characteristics and the advantages brought by the proposed modulation scheme are analyzed in terms of transmission power, state transition process, switching current and device losses. Moreover, the introduced modes and ZVS-on characteristics are verified on the 4kV/1kV 200kW experimental prototype. As a result, the converter’s loss can be decreased by up to 75% under light load, validating the efficiency advantage of the proposed modulation scheme.

Recently, the DC-DC solid-state transformer concept is becoming more and more popular for medium voltage applications. This architecture due to its modularity, has the potential to present high levels of reliability. However, there is lack of proper method for redundancy design in terms of the total cost of ownership. In this paper, we examine the reliability alongside the total cost of ownership of the architecture. An optimization method for choosing the number of redundant modules while applying the minimum total cost of ownership is provided. A case study is given to demonstrate the proposed method.

In electric vehicle inverter systems, the DC-link capacitor bank becomes a critical obstacle to high power density due to its large volume. DC-link capacitor bank commonly adopts a multi-core parallel structure. The challenges exist in the current sharing of parallel capacitor cores because of the imbalance of stray parameters in the busbars. A current sharing analysis method aiming at thermal stress for capacitor banks in high-power-density inverters based on the characteristic matrix is proposed in this paper. First, the design basis of DC-link capacitors is given theoretically. Then, the complex coupling impedance model between multiple ports on capacitor busbars is mathematically derived by the matrix method, revealing the current resonance phenomenon of parallel capacitor cores affected by stray parameters. Next, three capacitor banks are evaluated by the proposed current sharing model. The influence of capacitor core arrangement and terminal position on current sharing is explored, which can guide capacitor banks’ high-power-density structure and heat dissipation design. Finally, an experimental platform is built with customized capacitor samples. The experimental results are consistent with the analysis results of the model, verifying the proposed method.

Due to the low short circuit withstanding time, short-circuit protection (SCP) for SiC devices is challenging. The SCP is more difficult when multiple devices are connected in parallel, as the turn-off of one device locally may lead to the overstressing of others. To resolve this, a centralized SCP approach designed for parallel-connected devices is introduced. This method employs the instantaneous current from the common-source inductors in power modules as a key metric to simultaneously reduce the gate-source voltages across all devices. Additionally, the voltage drop across each power device is monitored to enable their timely turn-off. This two-stage strategy ensures a quick response and high noise immunity for SiC devices. The proposed approach, seamlessly integrated with the power converter’s controller, has been experimentally validated in a three-phase converter.

随着模块化多电平换流器(modular multilevel converter,MMC)应用领域的日益扩展,其子模块的开路故障引起了更多关注.为了诊断子模块开路故障,该文提出一种基于机器学习(machine learning,ML)的故障检测和定位策略.根据开路故障特性,文中选择子模块电容器电压作为故障检测的关键指标,然后引入一种从电压数据中提取时域特征的方法,以构造用于有监督学习分类器的样本.在对随机森林的分类器进行样本训练后,检测策略实时电压数据的特征量判断每个子模块的工作状态.所提出的策略可快速准确地定位故障子模块,而无需添加额外的传感器或构建电路的数学模型.最后,通过三相MMC实验平台验证所提出的开路故障检测策略的有效性.

Medium voltage high-frequency transformer (MVHFT), the key component in a MV solid-state transformer (MVSST), requires high reliability on its insulation parts. With the increase of power density, the insulation design of the MVHFT becomes a big challenge. The transformer needs to ensure both high breakdown (BD) strength for short-term fault tolerance and low partial discharge (PD) for long-term reliable operation. Therefore, beginning with the electric stress analysis and the anti-corona consideration, a mass-manufacturable insulation structure is proposed in this article. In the structure, an improved multishielding structure with an optimized shield potential design is used to reshape the electric field (E-field) distribution for higher BD strength and lower PD. And an end-winding stress grading (SG) method is proposed and modeled for both the structure and the material used. Finally, with the proposed insulation structure, a 100 kW PD free transformer prototype with 75 kV base insulation level (BIL) is built. It passed all insulation tests. Also, the prototype realizes high power density under a high insulation level, which reaches 11.2 kW/L.

Phase-corrected proportional resonant (PCPR) current controllers are mainly studied under high carrier ratio conditions. When applied to high-power converters with low carrier ratios, the system could be unstable or have poor dynamics without a proper parameter design. In order to illustrate both stability and dynamics to guide parameter design, bilateral Bode plots are tailored in this article that considers the correct negative jump direction at resonant frequencies. Then, this analysis tool verifies the feasibility of the phase correction angle set over 90°, especially under a carrier ratio below six. With the designed phase correction, the stability region of the carrier ratios is characterized as extending to the theoretical limit of one. Moreover, the resonant gain of PCPR is quantitatively designed considering the variation of carrier ratios by maximizing the bandwidth under guaranteed stability and margins. Finally, the simulations and experiments verify the enlarged stability region with the phase correction and improved dynamic performance with the proposed resonant gain design method.

Multisampling is a very effective and direct way to reduce control delay, which can greatly improve the bandwidth and stability margin. However, it will introduce high-frequency switching harmonics (SHs), resulting in low-frequency aliasing in regular sampling puslewidth modulation (PWM). The harmonic suppression of existing filters inevitably brings phase lag, which weakens the advantage of multisampling to reduce delay. To address the challenge of phase lag under multisampled aliasing suppression, this article proposes an antialiasing method with negligible phase lag for LCL-type grid-tied inverter. The analytical expression for the inverter-side current is derived, and the SHs symmetry and phase sequence characteristics are analyzed in detail. According to these characteristics, these SHs is converted into the harmonic components of integral multiple switching frequency after Park transformation. Moving average filter with phase-lead compen-sation is designed in dq frame to eliminate these harmonics. Theoretical analysis shows that the proposed method hardly introduces phase lag within the effective control frequency band. Finally, the experiment of a single-loop inverter-side current control verifies that the proposed method can effectively filter out the SHs with negligible phase lag, thus improving the dynamic response performance and control stability.

Switching loss of power semiconductor devices can be more considerable under multi-device-in-parallel packaging and high switching frequency operation. Zero-voltage-switching (ZVS) is a promising approach to eliminate switching loss. However, due to the extreme electromagnetic environment, it is still challenging to develop a feasible method to precisely control the switching of power devices at optimal ZVS moments. This paper thus proposes an optically-triggered adaptive soft-switching scheme by utilizing an intrinsic optical property of SiC MOSFET, the electroluminescence (EL) effect, to directly detect the optimal switching moment. A high-sensitivity and fast-response optical sensing circuit is designed, and the feasibility of the proposed scheme is validated on a synchronous Buck converter built on a customized PCB packaging power module.

In this article, a series-connected SiC MOSFETs-based medium voltage (MV) dual active bridge (DAB) converter featuring a low voltage difference among devices and high efficiency is proposed. In the developed DAB converter, the zero voltage switching-on characteristic is used to redesign the voltage balancing snubber circuits of the series-connected SiC MOSFETs. The snubber resistance is greatly reduced, whereas the snubber capacitance is increased, which realizes good voltage sharing and low switching-off loss of SiC MOSFETs. Furthermore, the operating modes and the operating characteristics of MV DAB converter with large snubber capacitors are derived in detail. Based on the above analysis, snubber capacitance and auxiliary inductance are optimized, taking into account the losses and voltage imbalance in the series-connected SiC MOSFETs. Finally, a 4 kV/1 kV experimental prototype is built and tested, and an experiment with up to 100 kW transmission power has been carried out. The results show that a maximum efficiency of 98.7% has been reached and the maximum voltage difference among SiC MOSFETs does not exceed 4%.

High-power converters operate at low carrier ratios (LCRs) featuring significant digital delay, making it challenging to suppress negative sequence current stably under unbalanced grid voltage. In this article, the worse amplification effect from negative sequence voltage to negative sequence current due to LCR under conventional proportional-integral (PI) control is first revealed and quantitatively explained with the complex transfer function. Furthermore, a phase-corrected proportional resonant (PR) controller is presented to suppress the amplification effect by the newly added pole and enhance the system stability by local phase correction (LPC). Meanwhile, a design scheme for phase correction angles is proposed to improve dynamics. Finally, simulation and experiments are provided to validate the negative sequence current elimination capability under various grid voltage sag depths as high as 100% at different carrier ratios as low as five, enhanced stability, and improved dynamic performance.

The overstress of the negative gate-source voltage of SiC MOSFET, even in a short period of time, could cause the threshold voltage drift of the device, resulting in increased on-state resistance. In this article, we propose an integrated gate driver to specially limit the peak negative gate voltage of SiC MOSFETs introduced by the crosstalk phenomenon and the reliable short-circuit protection. A simple auxiliary branch with bidirectional blocking capability is adopted in crosstalk voltage suppression and the negative peak voltage of the gate, introduced by common source inductor, is eliminated by the high impedance gate driving loop. Furthermore, the auxiliary circuit is reused to assist a two-step short-circuit protection of the device by identifying dc-link shoot-through current on the stray inductor. By rapidly reducing the gate-source voltage to a lower value when short-circuit happens, the short-circuit withstanding time of the device is prolonged, enabling a longer allowable detection time to confirm the fault event accurately. The proposed method comprehensively integrates the crosstalk voltage suppression and short-circuit protection together and is verified by the experiments.

Zero voltage switching (ZVS) is useful to increase power electronics efficiency but difficult to achieve due to the nonlinear parasitic capacitance of the power semiconductors and varying load current. This letter proposes a self-adaptive ZVS method by using the intrinsic electroluminescence (EL) property of SiC mosfets to automatically adjust the switching frequency in every switching cycle to retain the optimal ZVS in varying load current. A sensing circuit is developed to digitally utilize the EL to trigger ZVS and embodied in a customized PCB-embedded half-bridge power module. Experimental results demonstrate the effectiveness of the proposed optically triggered self-adaptive ZVS in a Buck converter. The proposed method is compatible with conventional PWM gate drives for various power electronic devices and applications.