The Democratic Republic of the Congo (DRC) has a high measles incidence despite elimination efforts and has yet to introduce rubella vaccine. We evaluated the performance of a prototype rapid digital microfluidics powered (DMF) enzyme-linked immunoassay (ELISA) assessing measles and rubella infection, by testing for immunoglobulin M (IgM), and immunity from natural infection or vaccine, by testing immunoglobulin G (IgG), in outbreak settings. Field evaluations were conducted during September 2017, in Kinshasa province, DRC. Blood specimens were collected during an outbreak investigation of suspected measles cases and tested for measles and rubella IgM and IgG using the DMF-ELISA in the field. Simultaneously, a household serosurvey for measles and rubella IgG was conducted in a recently confirmed measles outbreak area. DMF-ELISA results were compared with reference ELISA results tested at DRC’s National Public Health Laboratory and the US Centers for Disease Control and Prevention. Of 157 suspected measles cases, rubella IgM was detected in 54% while measles IgM was detected in 13%. Measles IgG-positive cases were higher among vaccinated persons (87%) than unvaccinated persons (72%). In the recent measles outbreak area, measles IgG seroprevalence was 93% overall, while rubella seroprevalence was lower for children (77%) than women (98%). Compared with reference ELISA, DMF-ELISA sensitivity and specificity were 82% and 78% for measles IgG; 88% and 89% for measles IgM; 85% and 85% for rubella IgG; and 81% and 83% for rubella IgM, respectively. Rubella infection was detected in more than half of persons meeting the suspected measles case definition during a presumed measles outbreak, suggesting substantial unrecognized rubella incidence, and highlighting the need for rubella vaccine introduction into the national schedule. The performance of the DMF-ELISA suggested that this technology can be used to develop rapid diagnostic tests for measles and rubella.

Serosurveys are useful for assessing population susceptibility to vaccine-preventable disease outbreaks. Although at-risk populations in remote areas could benefit from this type of information, they face several logistical barriers to implementation, such as lack of access to centralized laboratories, cold storage, and transport of samples. We describe a potential solution: a compact and portable, field-deployable, point-of-care system relying on digital microfluidics that can rapidly test a small volume of capillary blood for disease-specific antibodies. This system uses inexpensive, inkjet-printed digital microfluidic cartridges together with an integrated instrument to perform enzyme-linked immunosorbent assays (ELISAs). We performed a field validation of the system’s analytical performance at Kakuma refugee camp, a remote setting in northwestern Kenya, where we tested children aged 9 to 59 months and caregivers for measles and rubella immunoglobulin G (IgG). The IgG assays were determined to have sensitivities of 86% [95% confidence interval (CI), 79 to 91% (measles)] and 81% [95% CI, 73 to 88% (rubella)] and specificities of 80% [95% CI, 49 to 94% (measles)] and 91% [95% CI, 76 to 97% (rubella)] (measles, n = 140; rubella, n = 135) compared with reference tests (measles IgG and rubella IgG ELISAs from Siemens Enzygnost) conducted in a centralized laboratory. These results demonstrate a potential role for this point-of-care system in global serological surveillance, particularly in remote areas with limited access to centralized laboratories.

Isaac Newton famously observed that "if I have seen further it is by standing on the shoulders of giants." We propose that this sentiment is a powerful motivation for the "open-source" movement in scientific research, in which creators provide everything needed to replicate a given project online, as well as providing explicit permission for users to use, improve, and share it with others. Here, we write to introduce analytical chemists who are new to the open-source movement to best practices and concepts in this area and to survey the state of open source research in analytical chemistry. We conclude by considering two examples of open-source projects from our own research group, with the hope that a description of the process, motivations, and results will provide a convincing argument about the benefits that this movement brings to both creators and users.

We introduce an automated method to facilitate in-line coupling of digital microfluidics (DMF) with HPLC-MS, using a custom, 3D-printed manifold and a custom plugin to the popular open-source control system, DropBot. The method was designed to interface directly with commercial autosamplers (with no prior modification), suggesting that it will be widely accessible for end-users. The system was demonstrated to be compatible with samples dissolved in aqueous buffers and neat methanol and was validated by application to a common steroid-labeling derivatization reaction. We propose that the methods described here will be useful for a wide range of applications, combining the automated sample processing power of DMF with the resolving and analytical capacity of HPLC-MS.

The growth in field-programmable gate array (FPGA) capacity has outpaced improvements in serial processor speeds for the last decade and will continue for the foreseeable future. Unfortunately, as modern FPGAs have millions of logic elements and continue to grow, the compilation of designs can take hours or even days to complete. As a result, the runtimes of placement and routing flow have become a major concern for FPGA users and vendors alike. Roughly half the total compilation time is spent in the placement phase. Analytic placement algorithms solve the FPGA placement problem quickly. With an aim toward developing a scalable FPGA placement algorithm, we present a parallel analytic placement algorithm implemented on general-purpose computing graphics processing units (GPGPUs). The proposed analytic placer is scalable, that is, the placer maintains parallel efficiency as the problem size grows and number of parallel workers increase. Our algorithm is a parallelized version of the serial analytic placement algorithm StarPlace and achieves speedups of 13-31 times compared to this serial version. The proposed parallel algorithm is on average 78 times faster than the academic tool versatile place and route (VPR) when run in its fast, wirelength driven mode. The wirelength is on average 3% lower than VPR, with a 24% reduction in critical-path delay.

Placement run-times continue to dominate the FPGA design flow. Previous attempts at parallel placement methods either only scale to a few threads or result in a significant loss in solution quality as thread-count is increased. We propose a novel method for generating large amounts of parallel work for placement, which scales with the size of the target architecture. Our experimental results show that we nearly reach the limit of the number of possible parallel swaps, while improving critical-path-delay 4.7% compared to VPR. While our proposed implementation currently utilizes a single thread, we still achieve speedups of 13.3x over VPR.

Placement and routing run-times continue to dominate the automated FPGA design flow. As the size of FPGA architectures continue to grow exponentially, it remains critical to develop parallel tools for FPGA design where the amount of exposed concurrent work scales with the size of the designs to be synthesized. In this paper, we propose a novel algorithm for parallel placement, based on simulated annealing, where the amount of parallel work directly scales with the size of the net-list to be placed. Our approach concurrently evaluates and conditionally applies very large sets of non-conflicting swaps using common parallel computing primitives, including stream compaction, category reduction, and sort. While our design is suitable for targeting all modern parallel computing platforms, we present results from our implementation which targets NVIDIA's CUDA platform, where we achieve a mean speed-up of 19x over VPR with post-routing critical-path-delay and wire-length quality that matches or exceeds VPR. We believe that this work is an important step towards the development of a scalable, high-quality placement tool.

Since their inception, field programmable gate arrays have seen an enormous growth in usage because they can dramatically reduce design and manufacturing costs. However, the time required for placement (a key step in the design) is dominating the compilation process. In this paper, we take some initial theoretical steps towards developing an efficient genetic algorithm for solving the placement problem by developing suitable recombination operators for performing placement. According to Holland, when the genetic algorithm recombines two parent genotypes, the differences between them define a genotypic subspace, and any offspring produced should be confined to this subspace. Those recombination operators that violate this principle can direct a search away from the region containing the parent genotypes and this is contrary to the intended task for recombination. This is often detrimental to search performance. This paper contributes the development of an intuitive visualization technique that can be used to easily detect violations of the previous principle. The efficacy of the proposed methodology is demonstrated and it is demonstrated that many standard recombination operators violate this principle. The methodology is then used to guide the development of novel operators that exhibit substantial (and statistically significant) improvements in performance over standard recombination operators.

We introduce DropBot: an open-source instrument for digital microfluidics (http://microfluidics.utoronto.ca/dropbot). DropBot features two key functionalities for digital microfluidics: (1) real-time monitoring of instantaneous drop velocity (which we propose is a proxy for resistive forces), and (2) application of constant electrostatic driving forces through compensation for amplifier-loading and device capacitance. We anticipate that this system will enhance insight into failure modes and lead to new strategies for improved device reliability, and will be useful for the growing number of users who are adopting digital microfluidics for automated, miniaturized laboratory operation.

We present DropBot, a modular and extensible Digital Microfluidic (DMF) control instrument, and demonstrate compensation for parasitic capacitance and amplifier-loading effects, both critical to precise control of actuation voltage. We highlight quantitative metrics that are dynamically calculated by the system, including impedance, instantaneous drop velocity, and electrostatic driving force. We anticipate that these features will provide insight into the causes of device failure and lead to new strategies for improving experimental reliability and DMF device robustness.

While simulated-annealing is currently the most widely used method for performing FPGA placement, it does not scale to very large designs. Modern many-core architectures (including GPUs) offer a promising alternative to traditional multi-core processors for improving runtime performance. In this work, we propose a GPU-accelerated simulated-annealing variant for FPGA placement. Our approach uses the Star+ wirelength model along with a novel method of efficiently generating large sets of independent swap operations, providing a high level of parallelism. Speedups from 5.4-89.2× (median 20.2×) were achieved over a single-core CPU-only implementation.

When the genetic algorithm recombines two parent genotypes, the differences between them define a genotypic subspace, and any offspring produced should be confined to this subspace. Although this might seem insignificant, those recombination (or crossover) operators that violate this principle can direct a search away from the region (in genotypic space) that contains the two parent genotypes. This is contrary to the task for which the recombination operator was originally developed and can be detrimental, so this paper introduces a visualization that can be used to detect violations of this principle. The methodology also inspired the development of a different approach to recombining permutations, and a brief case study shows that an alternative recombination operator that does not violate this principle can be used to achieve a performance improvement over previous attempts to optimize Field-Programmable Gate-Array placements using a genetic algorithm. We believe that this technique will be invaluable for developing additional recombination operators.

To reduce the compilation times for Field Programmable Gate Arrays, genetic algorithms have been proposed for performing placement. However, the quality of solutions produced by these methods, so far, has been inferior to that produced by other search methods. In this paper, we show how traditional recombination operators, employed by the genetic algorithm when performing placement, fail to produce offspring solutions that are confined to the solution subspace defined by the parent solutions. This violates a fundamental principle that should govern the behavior of the recombination operator. We explore this flaw in detail, and propose a novel recombination operator that yields very statistically significant performance improvements, when tested with standard benchmarks.

In the FPGA design flow, placement remains one of the most time-consuming stages, and is also crucial in terms of quality of result. HPWL and Star+ are widely used as cost metrics in FPGA placement for estimating the total wire-length of a candidate placement prior to routing. However, both wire-length models are expensive to compute requiring O(nm) time, where n is the number of nets and m is the average net cardinality. This paper proposes using the massively multi-threaded architecture provided by GPUs to reduce the time required to compute HPWL and Star+. First, a specialized set of data structures is developed for storing net-connectivity information on the GPU. Next, a study is performed to determine how to best map the data structures onto the GPU to exploit the heterogeneous memories and thread-level parallelism that are available. Finally, a study is performed to determine what effect circuit size and net cardinality have on the speedups that can be achieved. Overall, the results show that speedups of as much as 160x over a serial CPU implementation can be achieved for both models when tested using standard benchmarks.

As the precise wirelength for a given placement can only be known after routing, accurate and fast to compute wirelength estimates are required for FPGA placement algorithms. Two of the more effective wirelength estimation models are HPWL [1] and Star+ [2]. However, both of these models are expensive to compute requiring O(nm) time, where n is the number of nets and m is the average number of blocks to connect. In this paper, we show that the time to compute HPWL and Star+ can be reduced by as much as 577x and 548x, re spectively, by exploiting the computational power available in modern Graphical Processing Units (GPUs). To reduce the runtime required to compute HPWL and Star+ we propose a set of data structures targeted specifically for the GPU archi tecture. We then investigate five different mappings of these data structures to the GPU to determine which mapping best exploits the heterogeneous memories and thread-level parallelism available on the GPU. Though our results are geared towards FPGA placement, they extend naturally to the less constrained VLSI placement problem.

A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic blocks, more efficient and scalable FPGA placement algorithms are needed. This paper investigates the feasibility of using hardware acceleration, in the form of FPGAs, to improve the performance of placement algorithms. An iterative algorithm is presented which exploits the fine-grain parallelism in routing individual nets. Overall, our results show that speedups of 3–4 times can be obtained, without sacrificing solution quality.

Global routing of macro cells remains an important but time-consuming step in the VLSI design cycle. Macro cells are large, irregularly sized parameterized circuit modules that typically contain large numbers of terminals that must be interconnected. The interconnection pattern for each set of terminals (net) that must be connected is a Steiner tree, and the primary sub-problem in the global routing of macro cells is to find a set of dissimilar, low-cost Steiner trees for each net that must be routed. In this paper, a two-phase, parallel (multi-processor) algorithm is proposed for quickly constructing a diverse pool of high-quality Steiner trees for routing of multi-terminal nets. In the first phase, a single Steiner tree is constructed using a heuristic, called Shrubbery. Then, in the second phase, a pool of dissimilar, high-quality trees are created from the original tree, by running multiple instances of a local search in parallel. Computational experiments performed on over 800 commonly used benchmarks show that running multiple instances of the local search in parallel results in near-linear speed-up over the serial case. Most importantly, the trees produced are both high-quality and dissimilar, allowing for numerous routing possibilities for each net.

Placement is one of the most time-consuming processes in automatically synthesizing and configuring circuits for field programmable gate arrays (FPGAs). In this paper, we present a hardware-accelerated iterative-improvement algorithm for performing placement. The design and evaluation of the accelerated algorithm is presented. Initial results indicate speedups of 3.5 times of hardware over software execution times. By taking better advantage of hardware parallelism, it is anticipated that speedups of at least an order of magnitude can be accomplished.

Field programmable gate arrays (FPGA) have become solutions of choice for embedded applications with small to medium production numbers. As a result, good CAD tools to support their use are in demand. This paper presents a solution to the FPGA placement problem. Some of the best solutions to date use iterative improvement heuristics such as simulated annealing. However,the run-times of these stochastic solvers becomes unacceptably long for performing placement on large FPGAs. Instead a deterministic iterative solver is proposed that is implemented in hardware. It implements a node-swap heuristic that starts from an initial random placement and iterates until it finds locally optimal solution. Initial results indicate speedups of 3-4 times over software.

Deterministic, Weak-scaling Parallelism for Wirelengthand Timing-driven FPGA Placement, suitable for Multicore and Manycore Architectures Christian Fobel University of Guelph, 2015 Advisors: Professor G. Grewal and Professor D. Stacey Field-Programmable Gate Arrays (FPGAs) enable rapid-prototyping of digital logic designs in-house, without the significant up-front expense of building custom fabrication facilities. However, as the number of resources on each new generation of FPGAs continues to grow rapidly, enormous pressure is placed on the development of algorithms to reduce hardware compilation times to maintain the competitive advantage of using FPGAs. Approximately half of the compilation time for FPGA designs is spent performing placement (which is NP-hard). Serial simulated annealing is typically used for placement in practice, where runtime unfortunately grows exponentially with circuit size to be placed. Therefore, development of parallel placement algorithms that can harness the increasingly abundant throughput of modern manycore architectures to improve runtimes remains a critical concern. Parallel FPGA placement methods in literature provide no theoretical basis for scalability, and reported runtime results suggest non-parallelizable work scaling with the size of the problem, preventing scaling. We propose a parallel FPGA placement methodology based on “completely parallelizable” patterns, leading to a weak-scaling isoefficiency function in Θ(p log p), while maintaining determinism. For placement, this means deterministic results where linear speedups are expected as the number of parallel worker threads (p) increases as long as the problem size (i.e., netlist size) grows accordingly. Using parallel patterns, we also propose the first scalable algorithms for timing analysis, which are ideally suited for modern manycore architectures, such as GPUs. Our experimental results show that our proposed wirelengthand timing-driven placement tools achieve mean absolute runtime improvements of 19× and 31×, respectively, on a commodity GPU over a state-of-the-art academic placer (VPR). With respect to quality, our wirelengthdriven tool improves solution quality by 5% over VPR, while our timing-driven placer improves critical-path delay by 20% compared to our proposed wirelength driven method. Our results also indicate increased parallel efficiency as the size of the problem grows. Since both the parallel worker count on modern commodity parallel architectures and the number of resources available on modern FPGAs are growing rapidly, weak-scaling is an ideal fit for parallel FPGA placement to provide sustainable performance for future FPGA designs and manycore architectures.