In this paper, a novel synthesizable temperature sensor for FPGA devices, which uses DSP-slices instead of LUTs, is presented. The correlation between the delay of the critical path and the temperature of a DSP-slice is exploited to implement a ring oscillator, whose oscillation frequency is used to estimate the local die temperature. In contrast to previously proposed synthesizable temperature sensors based on ring oscillators implemented with LUTs, the proposed DSP-based temperature sensor has a smaller footprint. The complete synthesizable temperature sensor, including the ring oscillator and the required time-to digital converter, only requires three DSP-slices. An evaluation using a programmable climate chamber and a Virtex-6 FPGA evaluation board is presented. The DSP-based temperature sensor provides similar accuracies (i.e., +/- 0.5 degrees C) than LUT-based temperature sensors, while greatly improving the resolution and temperature sampling rates depending on the selected configuration. Finally, by using the proposed temperature sensors together with several internal hardware heat generators, a maximal temperature gradient of 9 degrees C was measured on the FPGA die. (C) 2017 Elsevier B.V. All rights reserved.

Current research on synthesizable temperature sensors, using the reconfigurable logic of the FPGA to measure temperature anywhere on the FPGA, ueses an oscillating, temperature dependent route on the FPGA. These LUT-based routes require a complex calibration process and have a large footprint on the die. The proposed synthesizable temperature sensor uses DSP-slices to reduce the calibration overhead and the footprint as well. The sensor can achieve a resolution of up to 0.12 ^∘ C, depending on configuration. A sample rate of up to 1040 samples per second is feasible, in the fastest configuration. The sensor was evaluated and compared. The sensor is more stable, easier to calibrate and features a smaller footprint. This allows a higher density of temperature sensors than before. It uses 45 FF, 69 LUTs, 6 Shift-Registers (SRL32) and 4 DSP-slices to realize a fully digital, synthesizable temperature sensor, including a calibration circuit, a reading circuit and a buffer structure to save multiple data samples.

Computational-intensive algorithms are often realized with dedicated or customized hardware architectures suffering from high development costs and low flexibility thereafter. Instead, modern multicore and manycore processors can execute a diversity of software applications (e.g, driver assistance systems) written in portable high-level programming languages resulting in less porting effort at lower costs for power-consumption tolerant fields. For instance, the Intel Xeon Phi manycore processor featuring 61 cores offers not only a high theoretical peak performance but also a supportive tool chain for the software development in high-level programming languages. In contrast to traditional general-purpose multicore processors, this manycore architecture, however, exhibits different processor characteristics, inter-core communication topologies, and instruction sets. In this paper, we introduce the parallel implementation of a histogram of oriented gradients algorithm for pedestrian detection. Using a parallel semi-global matching algorithm as well, serving as an additional driver assistance algorithm, we present an in-depth performance analysis case study on the Intel Xeon Phi and also note distinct characteristics of this target platform. To allow a fair comparison, we not only rate an Intel Xeon 16-core general-purpose processor, but also present a platform comparison to customized hardware architectures.