A CMOS power amplifier (PA) optimized for high gain, high-power, and broadband operation is proposed for subTHz radar applications. The transistor layout is optimized to enhance both maximum oscillation frequency (f max $_{\text {max }}$) and output power. An interstage matching network based on a modified transformer T-model is proposed to achieve a dual-band response. Moreover, a slotline-based power divider/combiner with greater design freedom is proposed to facilitate broadband impedance matching and power division/combination. By integrating the dual-band impedance matching networks with the single-band power divider/combiner, the PA achieves broadband operation, effectively alleviating the gain-bandwidth trade-off near $\boldsymbol{f}_{\text {max }}$. Fabricated in a $40-\text{nm}$ CMOS technology, the proposed PA achieves a measured $20-\text{dB}$ gain and a saturated output power of 4.5 dBm at 194 GHz, with a $6-\text{dB}$ bandwidth of $187-224 \text{GHz}$. To the best of the authors' knowledge, this work demonstrates the broadest reported bandwidth for a CMOS PA operating beyond 200 GHz.

Terahertz (THz) technology has emerged as a promising enabler for future sixth-generation (6G) communications, integrated sensing and communication (ISAC), and biomedical imaging applications. Among the available semiconductor technologies, CMOS is particularly attractive because of its low cost, high integration density, and compatibility with mass production. However, realizing high-performance THz systems in CMOS remains challenging due to limited transistor speed, severe passive losses, low antenna efficiency, and limited output power. This article reviews recent advances in CMOS THz electronics and highlights how cross-level innovations spanning transistor modeling, circuit design, antenna engineering, heterogeneous integration, and system architectures can address these challenges. Key developments, including electromagnetic-based transistor optimization, THz amplifiers, phase-locked loops, dielectric-resonator antennas, and system-on-package heterogeneous integration, are discussed. Representative communication and sensing systems are also presented to demonstrate the integration of these technologies into practical THz applications.

This work presents a 230-GHz 1 x 2 phased-array signal source (SS) that integrates a voltage-controlled oscillator (VCO), two 360 degrees phase-shifting amplifier-frequency-multiplier chains (AMCs), and two high-resistivity Si dielectric resonator antennas (DRAs). Each AMC comprises a driver amplifier (DA) and a frequency tripler (FT). The DA employs a phase-shifter-embedded impedance-matching network (IMN) that simultaneously provides balun functionality, >120 degrees phase shifting, and impedance transformation, effectively reducing power loss and chip area. The FT employs a fundamental voltage-tuning technique to tolerate higher input power without voltage breakdown issues, improving the output power by 2.5dB. The DRA utilizes a tapered feeding structure to broaden the bandwidth (BW), achieving an antenna gain of 3.9 dBi and a fractional BW of similar to 10% at 230 GHz. Fabricated in a 40-nm CMOS process, the proposed SS provides frequency tuning from 215 to 240 GHz, an equivalent isotropically radiated power (EIRP) of 8.5 dBm, and a 60 degrees beam-steering range at 225 GHz.

An ultra-wide band (UWB) antenna employing spoof surface plasmon polariton principles is introduced, offering tunable single- and dual-band rejection. Inserting slot resonators into the SSPP feed achieves band-notching. The achieved notched band can be tuned by employing varactor diodes across the slots. Single and dual-notch bands have been achieved using two varactor diodes. Tunable notches cover the frequency range of ultra-wideband systems, starting from 3.1 to 10.6 GHz. Notch band reconfigurability and notch bandwidth controllability are achieved by designing the slot geometry and the varactor diode capacitance, which change the circuit model's R, L, and C component values to achieve the intended quality factor and, thus, the rejection bandwidth for a specific frequency band. The proposed idea works for all notch frequencies in the UWB range. The rejection bandwidth can be tuned from 398 to 1430 MHz with superior selectivity. Moreover, the proposed SSPP-based monopole antenna can easily be integrated with active devices due to the dual-conductor structure of the feeding SSPP transmission line. The proposed SSPP-based UWB antenna shows a measured peak gain of around 4 dBi. To the authors' knowledge, notch bandwidth controllability and tuning across a wide range of frequencies have not been reported previously.

This work presents a 60-GHz on-off keying (OOK) transceiver (TRX) designed for a high-speed, low-cost, short-range wireless interconnect. The TRX integrates a 60-GHz OOK transmitter and receiver, both realized in a 90-nm CMOS technology, with antennas fabricated on a low-cost FR4 printed circuit board (PCB) using chip-to-PCB interconnects. The TX achieves an output power of 3.7dBm, and the RX provides a conversion gain of 24.9dB at 60GHz. The antenna employs an aperture-coupled patch structure, providing a 3.2dBi of gain at 64GHz and a 3-dB bandwidth spanning 59-70GHz. The chip-to-PCB interconnect, utilizing gold-stud bumps and solder balls, is optimized to ensure a smooth impedance transition from the chip to the PCB, achieving an insertion loss of less than 3dB and a return loss of better than -10dB from DC to 146GHz. The insertion loss is only 0.6dB at 60GHz. The proposed 60-GHz OOK TRX delivers a 4.1-Gb/s data rate over a 6-cm link while maintaining a bit-error rate (BER) below 10(-3) for a 2(7) - 1 pseudorandom binary sequence. It achieves a distance-normalized energy efficiency of 5.6 pJ/bit/cm.

This work proposes a 200-GHz signal source for sub-THz biomedical imaging applications. The signal source integrates a fundamental voltage-controlled oscillator (VCO), a power amplifier (PA), and a frequency doubler. Its architecture is optimized for a wide tuning range and high output power. The PA amplifies the 100-GHz signal generated by the VCO, providing sufficient power to drive the frequency doubler, which then multiplies the input frequency to produce the desired 200-GHz output. Implemented in a 40-nm CMOS technology, the proposed signal source delivers an output power of -0.3 dBm at 181.4 GHz with a tuning range of 8.5%. The signal source only consumes 172 mW from a 0.9-V supply.

A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistors maximum oscillation frequency fmax from 239.7 to 367.5 GHz. Furthermore, a Gmax-peak-offset-matching technique is proposed to simultaneously optimize active transistors and passive matching networks, significantly increasing the gain by 3.5 dB. Implemented in a 65-nm CMOS technology, the proposed THz amplifier achieves a measured gain of 30.9 dB at 302.5 GHz with an output saturation power of -5.3 dBm while only consuming 35.4 mW from a 1.1 V supply. To the best of the authors knowledge, this work exhibits the first experimental validation of the EM modeling approach and achieves the highest reported gain above 200 GHz in bulk CMOS technologies.

A 240-GHz direct-conversion transmitter (TX), consisting of an LO chain and fundamental I/Q mixers, is proposed for sub-THz communication applications. The LO chain integrates phase-shifter-embedded impedance matching networks (IMNs) and frequency tripler with an optimized harmonic IMN, delivering I/Q LO signals at 240 GHz with high output power, 360 degrees phase shifting range, and I/Q phase calibration capability. The I/Q mixer incorporates two transformer baluns for I/Q signal combining and ground-shielding structures, ensuring layout symmetry and reducing coupling. This can significantly enhance the image rejection ratio (IMRR) and suppress LO feedthrough (LOFT). Fabricated in a 40-nm CMOS process, the proposed TX provides an output power of -11.7 dBm at 240 GHz with a 3-dB bandwidth (BW) from 224 to 244 GHz. It achieves LOFT suppression and IMRR better than -17.7 and -16.3 dBc, respectively, within the 3-dB BW.

A 230-GHz phase-shifter-embedded (Delta phi-embedded) frequency tripler (FT) for sub-THz phased-array applications is proposed in this work. The FT's driver amplifier incorporates Delta phi-embedded impedance matching networks, which can simultaneously realize >120 degrees phase shifting, impedance transformation, and single-ended to differential conversion, effectively reducing insertion loss and chip area. Moreover, a fundamental voltage tuning technique is proposed to mitigate the transistor's voltage breakdown limitations. This enables the FT to reliably handle higher input power, significantly enhancing the output power by 2.5 dB. Fabricated in a 40-nm CMOS process without ultra-thick metal layers available, the proposed FT can deliver an output power of 3.5 dBm and conversion gain of 0.5 dB at 225 GHz with a 3-dB bandwidth from 214 to 246 GHz while consuming 230 mW from a 0.9-V supply. The phase-shifting range can exceed 360 degrees across the 220-to-245 GHz frequency range.

A 340-GHz THz phase-locked loop (PLL) composed of an 85-GHz integer-N charge-pump PLL (CPPLL) and a 340-GHz frequency quadrupler (FQ) is proposed for THz communication applications. The FQ utilizes an optimal harmonic impedance matching technique to provide high conversion gain and output power. Given the targeted 340-GHz output frequency, this FQ enables the CPPLL to operate at a lower frequency of 85 GHz, significantly improving the THz PLL's phase noise (PN) and frequency tuning range. Implemented in a 40-nm CMOS technology without ultra-thick metal layers, the proposed THz PLL can be locked from 324 to 360 GHz. It achieves an output power of -6 dBm, a reference spur of -35.5 dBc, a PN of -87.4 dBc/Hz at the 1-MHz offset, and an RMS jitter of 145 fs integrating over 10 kHz to 100 MHz at 340 GHz. The THz PLL exhibits the highest figure of merit beyond 300 GHz.

This work presents a binary coding metasurface operating at 0.35 THz, implemented using glass-based integrated passive device (IPD) technology. The metasurface consists of binary elements with identical reflection amplitudes but a 180-degree phase difference, enabling beam-splitting functionality through a periodic coding sequence. A fabricated prototype is experimentally validated using a custom-built measurement setup, with results showing strong agreement with full-wave simulations. The demonstrated glass IPD-based terahertz metasurface offers a cost-effective and scalable solution for next-generation wireless communication systems.

A 230-GHz phase-shifter-embedded ( Delta phi -embedded) frequency tripler (FT) for sub-THz phased-array applications is presented in this work. A fundamental voltage tuning (FVT) technique is proposed to address the CMOS breakdown voltage limits to shape the drain voltage waveform by adjusting the fundamental impedance, thereby lowering the drain-to-gate voltage. This allows for higher input power handling and yields a 2.5-dB increase in output power. A modified voltage-domain power series is utilized to estimate the FT's output swing, enabling designers to assess whether the FT exceeds the breakdown limit. Moreover, the FT's driving amplifier features Delta phi -embedded impedance matching networks that can deliver over 120 degrees phase shifting, impedance transformation, and single-ended-to-differential conversion, effectively reducing insertion loss and chip area. Fabricated in a 40-nm CMOS without ultrathick metal layers, the proposed FT provides 3.5-dBm output power and 0.5-dB conversion gain at 225 GHz, with a 3-dB bandwidth from 214 to 246 GHz. A phase-shifting range exceeding 360 degrees is obtained across the 220-245-GHz frequency range. The FT consumes 230 mW from a 0.9-V supply. To the best of the authors' knowledge, the proposed FT demonstrates the highest figure of merit above 200 GHz reported thus far.

This paper presents the design of sub-THz and THz integrated circuits in a 40-nm CMOS process without ultra-thick metal layers. The demonstrated circuits include a 126-GHz power amplifier delivering 11.2 dBm output power, a 234.9-GHz fundamental oscillator, a 340-GHz LO source supporting full 360 degrees phase shifting, and a 324-360-GHz phase-locked loop providing -6 dBm output power. The circuit architectures are carefully optimized, and advanced design techniques, such as transistor layout optimization, multifunctional impedance matching networks, and optimal harmonic impedance tuning, are employed to enhance performance significantly. These key building blocks are well-suited for next-generation sensing and 6G wireless communication applications.

THz CMOS designs are challenging due to low supply voltages, limited transistor speeds, lossy silicon substrates, and unfriendly back end of the lines. In this talk, we will delve into the design challenges of THz electronics using CMOS technologies for both THz sensing and communication applications. We will show our efforts to address the issues mentioned above from the device-level transistor layout optimization using an electromagnetic modeling approach for enhancing fmax from 288 to 394 GHz in a 40-nm CMOS technology up to the system-level THz imaging demonstration with the spatial resolution of 1.4 mm at 336 GHz.

A 340-GHz compact terahertz (THz) amplifier-frequency-multiplier chain (AMC) offering a full 360 degrees phase shifting range for phased-array applications is proposed in this paper. The AMC comprises an 85 -GHz phase-shifter-embedded (Delta phi-embedded) power amplifier (PA) and a high-output-power frequency quadrupler (FQ). The PA is equipped with multifunctional impedance matching networks (M-IMNs) that can simultaneously provide balun, impedance transformation, and phase-shifting functions. Analytic expressions have been derived to provide design guidelines for the M-IMNs. With the integrated M-IMNs, the proposed PA can concurrently deliver high output power and a phase shift exceeding 90 degrees in a compact chip area. The proposed FQ can achieve optimal impedance matching at second and fourth harmonic frequencies, leading to the output power enhancement of 2.6 dB. Furthermore, the output phase of the PA is quadrupled by the FQ, resulting in the output signal of the AMC with a full 360 degrees phase-shifting capability. A measurement setup for characterizing the phase of a THz signal is also presented. Implemented in a 40-nm CMOS technology without ultra-thick metal layers available, the proposed THz AMC achieves a peak output power of -3.5 dBm at 368 GHz with a conversion gain of 1.8 dB and a 3-dB bandwidth from 340 to 376 GHz. The output phase can continuously vary over 360 degrees within the 324 to 346 GHz frequency range. The phase noise of the output signal at 346 GHz is -105 dBc/Hz at a 10-MHz offset frequency. The proposed 340-GHz AMC consumes 215.1 mW from a 0.9-V supply.

A 235-GHz amplifier-frequency-multiplier chain (AMC) composed of a cascode power amplifier (P A) and a frequency tripler (FT) for 6G applications is proposed in this work. The proposed FT integrates an optimal output harmonic impedance matching network, which can simultaneously achieve optimal impedance matching at both the fundamental and third harmonic frequencies, leading to a 5.7-dB enhancement in output power. Implemented in a 40-nm CMOS technology without ultra-thick metal layers available, the proposed AMC can deliver a peak output power of -2.7 dBm at 234 GHz with a 3-dB bandwidth from 218 to 252 GHz. Compared to prior works, the proposed AMC shows the highest figure of merit.

A 240-GHz wideband low-noise amplifier (LNA) incorporating high-speed customized transistors and dual-peak-G(max) cores is proposed in this work for 6G applications. The customized transistors, designed and modeled using an electromagnetic modeling approach, reduce the gate resistance and the drain-to-gate capacitance, enhancing f(max) from 288 to 394 GHz. The dual- peak-G(max) core utilizes a reciprocal embedding network consisting of two pre-embedding transmission lines and a DC-isolated Y-embedding transmission line to achieve maximum gain conditions at 221 and 261 GHz simultaneously, enabling the LNA to exhibit wideband characteristics efficiently. Implemented in a 40-nm digital CMOS technology, the proposed LNA shows a measured power gain of 16.2 dB at 220 GHz with a 3-dB bandwidth spanning from 208.6 to 223.6 GHz and a simulated noise figure of 11.5 dB while only consuming 34.7 mW from a 0.9-V supply. The measured output 1-dB compression point is -5.3 dBm at 220 GHz.

A phase-shifter-embedded (Δφ-embedded) power amplifier (PA) incorporating multifunctional Δφ-embedded impedance matching networks (IMN) is proposed for 6G applications. The Δφ-embedded IMN can realize impedance transformation, execute a single-ended to differential conversion, and simultaneously provide a phase shift without requiring additional circuits. Hence, the insertion loss, occupied chip area, and power dissipation can be reduced. Realized in a 40-nm digital CMOS process, the proposed PA can provide a maximum saturated output power of 10.2 dBm and a phase-shifting range wider than 90° from 75 to 89 GHz. The power consumption is 151 mW from a 1.1-V supply.

The challenges of THz electronics in CMOS technologies for THz sensing and communication applications are addressed in this work, focusing on device- level design to system integration approaches. State-of-the-art THz circuits, components, design methodologies, and system demonstration were proposed, including a 40-nm-CMOS transistor layout design using an electromagnetic modeling approach, a 340-GHz higher-order-mode high-gain dielectric resonator antenna, a 340-GHz CMOS heterodyne receiver, a 340-GHz heterogeneously-integrated THz transmitter with 2x25 antennas, a THz heterogeneously-integrated platform with low-loss single-band, dual-band, and broadband interconnects, and a THz transmissive imaging system with a spatial resolution of 1.4 mm at 336 GHz.

A compact and low-cost THz system-on-package (SoP) heterogeneous integration platform is proposed in this work. Different chips fabricated in different technologies can be integrated together onto a common low-loss and low-cost integrated-passive-devices (IPD) carrier using low-loss chip-to-IPD THz interconnects. On-carrier low-loss microstrip lines, coplanar waveguides, and substrate-integrated waveguides (SIW) are used to communicate signals between these different chip modules. Low-loss SIW filters on the IPD carrier are employed to filter out undesired spurs, harmonics, noise, and interference signals. Experimental results show that the proposed single-band, dual-band, and broadband THz interconnects from a 0.18-$\mu$ m CMOS chip to an IPD carrier can give insertion loss of 2, 2.8 and 3.2 dB, and lower than 3.7 dB at 306.5, 140 and 324.5 GHz, and from 140 to 330 GHz, while keeping the return loss better than 10 dB from 256.5 to 330, 140 to 182 and 280 to 330, and 140 to 330 GHz, respectively. The measured insertion loss of a fourth-order Chebyshev SIW filter realized in a commercially-available GaAs IPD technology is 3.6 dB at 327.5 GHz. With the proposed THz heterogeneous integration platform, the unique advantages of these different chip modules realized in different technologies can be utilized to carry out compact, high-performance, low-cost, and high-integration THz systems for sensing and communication applications.