Dialogue systems have the potential to change how people interact with machines but are highly dependent on the quality of the data used to train them. It is therefore important to develop good dialogue annotation tools which can improve the speed and quality of dialogue data annotation. With this in mind, we introduce LIDA, an annotation tool designed specifically for conversation data. As far as we know, LIDA is the first dialogue annotation system that handles the entire dialogue annotation pipeline from raw text, as may be the output of transcription services, to structured conversation data. Furthermore it supports the integration of arbitrary machine learning models as annotation recommenders and also has a dedicated interface to resolve inter-annotator disagreements such as after crowdsourcing annotations for a dataset. LIDA is fully open source, documented and publicly available [ https://github.com/Wluper/lida ]

Classification tasks are usually analysed and improved through new model architectures or hyperparameter optimisation but the underlying properties of datasets are discovered on an ad-hoc basis as errors occur. However, understanding the properties of the data is crucial in perfecting models. In this paper we analyse exactly which characteristics of a dataset best determine how difficult that dataset is for the task of text classification. We then propose an intuitive measure of difficulty for text classification datasets which is simple and fast to calculate. We show that this measure generalises to unseen data by comparing it to state-of-the-art datasets and results. This measure can be used to analyse the precise source of errors in a dataset and allows fast estimation of how difficult a dataset is to learn. We searched for this measure by training 12 classical and neural network based models on 78 real-world datasets, then use a genetic algorithm to discover the best measure of difficulty. Our difficulty-calculating code ( https://github.com/Wluper/edm ) and datasets ( http://data.wluper.com ) are publicly available.

A design and integration of highly accurate Parametric Measurement Unit (PMU) with 600MHz Driver, Comparator, and an Active Load (DCL) is presented in this paper using 0.5um BiCMOS process. These circuits are necessary components of Automated Test Equipment (ATE) systems used to test ICs and are often referred to collectively as the Pin Electronics (PE). PMUs are high accuracy low bandwidth circuits that have to drive a range of capacitive loads. The need for high accuracy requires the use of feedback and high gain operational amplifiers. The trade-offs to be made in these circuits is between accuracy and settling time. Better accuracy requires higher gain which requires more aggressive compensation which increases settling time. A design approach that strikes a balance between DC accuracy and settling time is proposed. Design techniques are used to minimize the output capacitance of the PMU allowing its integration onto the 600MHz DCL in the circuit that affect the speed of the test path. The measured data from the fabricated chip shows the minimum open loop gain of 42dB for desired linearity error with 600pF capacitor pole compensation capacitor in high current range. The design has been successfully integrated on 1580um by 600um BiCMOS silicon area with less than 150uV measured voltage error and less than 0.001% measured current error.

A design approach of a Parametric Measurement Unit (PMU) is presented along with integration onto the same Integrated Circuit (IC) with 600MHz Driver, Comparator, and Active Load (DCL). These circuits are necessary components of many Automated Test Equipment (ATE) systems used to test ICs and are often referred to collectively as the Pin Electronics (PE). PMUs are high accuracy and low bandwidth circuits that have to drive a range of capacitive loads. The need for high accuracy requires the use of feedback and high gain operational amplifiers. The tradeoff to be made in these circuits is between accuracy and settling time. Better accuracy requires higher gain which requires more aggressive compensation which increases settling time. A design approach will be proposed that strikes a balance between DC accuracy and settling time. In areas of the circuit that affect the speed of the test path, novel design techniques are used to minimize the output capacitance of the PMU allowing its integration onto the 600MHz DCL.