In emerging blockchain-based IoT systems, highly flexible and energy-efficient hash function hardware design is necessary to maintain the operation of diverse blockchain networks. Accordingly, a coarse-grained reconfigurable array (CGRA) is the most optimal architecture for implementing hash functions; however, current CGRA-based works still have slow speeds and low energy efficiency. To solve these problems, this paper proposes a Coarse-Grained Linear Array (CGLA), upgrading from the CGRA, to perform multiple hash functions with high speed and energy efficiency. To achieve that goal, three main ideas are proposed: a self-updating data method, an expandable processing element array (PEA), and an efficient arithmetic logic unit (ALU) dedicated to hash functions. Our CGLA has been successfully implemented on a TySOM-3A FPGA. Evaluations on 45nm ASICs show that the CGLA is 2.8-8.7 times more power efficient than GPUs, and 1.3-17.8 times and 1.9-44.5 times better in throughput and energy efficiency than previous CGRAs.
This paper proposes a 3D-IC design for AI-Vision SoCs to address the limitations of performance and functionality inherent in using traditional 2D-ICs within a limited form factor. We defined criteria for subsystem partitioning focused on performance, power, and area (PPA) and implemented a 3D-IC with an efficient subsystem top and bottom die layout. The implementation results show a significant reduction in die area to approximately 59.7% of a comparable 2D-IC, including a 3D-I/O overhead of 0.285 mm 2
Implementation of deep learning models is constrained by different memory and computational requirements. While significant progress has been made in enhancing the processing element performance, the complete system throughput largely depends on memory transfer from the off-chip interfaces. This work proposes a complete on-chip solution for accelerator implementation on devices with resource constraints. We propose batch-wise clustering of the weights of DL models and in-situ generation of weights to be fed to the acceleration for the computations as per the model specifications. This architectural change is further complemented by the popular technique of zero-skipping. Experimental observations indicate that an average reduction in model parameters of more than 26% can be obtained at a 10% reduction in accuracy for three benchmark models extensively used in the literature.
Through-Silicon Vias (TSVs) are widely used as a solution to solve interconnection and power delivery issues of 3D integrated circuits. However, as manufacturing technology becomes finer, the reliability of TSVs has emerged as a significant challenge. This paper proposes a signal shifting-based reusable redundant TSV structure for infrastructure TSVs. Unlike conventional approaches where redundant TSVs left after repairs in signal-shifting structures remain unused, the proposed structure enables their utilization for repairing infrastructure TSVs. By ensuring that the proposed structure does not impact signal TSVs while utilizing redundant TSVs for infrastructure TSV repairs, it significantly enhances the reliability of semiconductors.
This paper presents an SRAM-based input bit configurable pulse-train computing-in-memory (CIM) macro for edge devices. The proposed macro computes matrix-vector-multiplications (MVM) in a bit-wise manner, generating pulse trains to overcome the limited signal margin and variations occurring in analog time-domain SRAM-based CIM macros. Furthermore, the system architecture comprises an error-free dynamic OR gate discharge computation, effectively addressing the non-linearity associated with analog computation methods. It also incorporates a dual pulse counter, which enhances the throughput of the system while maintaining high energy efficiency. The prototype 4Kb pulse train SRAM CIM was implemented using 28-nm CMOS technology, achieving 226.14 TOPS/W energy efficiency and a 5.14x increase in area efficiency compared to the state-of-the-art reaching 5.782 TOPS/mm2.
In recent years, transformer-based models have achieved excellent performance in various fields such as computer vision and language processing. Specifically, vision transformer (ViT) models outperform conventional convolutional neural networks (CNNs) in image classification tasks by achieving higher accuracy. However, ViT-based models often require more parameters than CNNs, making efficient deployment challenging in memory-constrained environments such as mobile devices. For example, the peak memory required in the output header layer of EfficientViT was 39.32 Mb. Deploying such a layer on the Zynq-7000 XC7Z045 FPGA board requires off-chip memory access, leading to inefficient power consumption. To address these issues, we applied a low-rank approximation method to reduce the memory requirements of the EfficientViT-B1 model. Our proposed method using the EfficientViT-B1 model on the ImageNet dataset achieved performance with only a 0.43% accuracy drop without requiring DRAM access.
This paper presents a 1-bit third-order delta-sigma modulator for high-resolution sensors. By sharing digital-to-analog converter (DAC) and sampling capacitors, we mitigate the influence of KT/C noise, while enhancing resolution through a chopping technique and internal feedback loop. The prototype chip is fabricated in a 28-nm CMOS process with an area of 0.122 mm 2 . It achieves a peak signal-to-noise ratio (SNR) of 83.6 dB and a peak signal-to-noise and distortion ratio (SNDR) of 81.6 dB in a 20 kHz signal bandwidth while consuming 13.3 mW from a 1.8 V power supply.
A compact VCSEL driver circuit supporting PAM4 signals for high-speed communications is proposed. The proposed circuit achieves a wide bandwidth with active inductors that can supply a large amplitude voltage and an active feedback that applies strong negative feedback. The active inductor with level shift enhances high linearity in the output signal by overcoming limitations of the circuit bias conditions. This configuration without spiral inductors reduces the circuit area by 49% compared to the circuit designed with inductive shunt peaking. The proposed circuit was fabricated in 0.18-mu m CMOS technology. It operates at a bit rate of 6 Gb/s, consumes 124.2 mW, and occupies an integrated area of 0.115 mm(2).
The bottleneck problem arises from the internal crossbar architecture within the HBM. Challenges related to the internal crossbar’s bandwidth in HBM primarily revolve around efficiently utilizing the memory’s considerable bandwidth on Field-Programmable Gate Array (FPGA) platforms. To tackle this issue, we propose the Multi-flit HBM Crossbar(MHC), which offers customized interconnections tailored for FPGA HBM boards, targeting high performance. The crossbar stage is designed using the Butterfly-Fat-Tree(BFT) structure, with multi-flit data format adoption. The effectiveness of MHC has been demonstrated through its application on the Xilinx Alveo U280 board. We have enhanced bandwidth across diverse addressing policies and noted that employing multi-flit leads to notable band-width improvements, especially with increasing burst lengths.
This paper presents a novel piecewise linear (PWL) approximation method for designing a highly precise nonlinear activation function tailored for hardware implementation of inference models. It is developed as an Adaptive Step-Size-based Recursive Algorithm (ASRA) method, incorporating the maximum allowable error (epsilon) as an input parameter. PWL functions are realized with minimal computational overhead, utilizing only addition operations and coefficient memory, thus avoiding multiplications. With fewer resources, the proposed method allows for the accurate approximation of nonlinear functions. The hardware implementation uses a Synopsys Design Compiler with a TSMC 90-nm library. Performance comparison in terms of area, delay, and power consumption demonstrates the effectiveness of the proposed approach.
This paper presents a 60 GHz On-Off Keying (OOK) receiver with a 7.7 GHz baseband bandwidth for high-speed wireless communications. The receiver consists of a low noise amplifier (LNA), an envelope detector, and a limiting amplifier with DC offset cancellation. The envelope detector directly detects the OOK envelope signal from the LNA output signal, which helps minimize the power consumption. The channel bandwidth is widened via two techniques; a split inductor at the LNA load and a feedforward capacitor at the baseband limiting amplifier. Designed in a 65-nm CMOS process, the receiver consumes 17.5 mW from a 1 V supply, showing a conversion gain of 17.5 dB and a baseband bandwidth of 7.7 GHz, supporting up to 10 Gbps data rate.
The growing adoption of Deep Learning (DL) models at the network edge necessitates robust security measures. Image preprocessing, a common technique for securing DL models, often involves shuffling the pixels of training images before feeding them to the model. In this work, we found that the shuffle-then-flip method offers superior resilience compared to the shuffle-only method. We also investigate the effectiveness of the shuffle-then-flip preprocessing technique in enhancing the security of models against attacks.
Accurate State of Charge (SoC) estimation is essential for efficient battery management systems (BMS). In this study, we propose a novel hybrid neural network architecture, combining the Informer and Long Short-Term Memory (LSTM) networks. Our hybrid network captures temporal dependencies and nonlinear characteristics inherent in battery data, enhancing sequence integration capabilities and computational efficiency. Experimental results on battery datasets demonstrate the effectiveness of our approach, with the proposed method achieving a maximum Mean Absolute Error (MAE) of 1.395% and a maximum Root Mean Square Error (RMSE) of 1.593%. Our findings suggest that the Informer-LSTM hybrid network holds promise for improving battery SoC estimation accuracy and enhancing battery management systems.
High-bandwidth memory (HBM) has been developed for high-performance computing. For high reliability, some soft errors are corrected by the error correcting codes (ECC) on the memory die. However, the error correctability of on-die has limitations, necessitating methods to achieve higher reliability. A novel method is proposed that utilizes zero parts in DQ-data as ECC check bits and uses metadata as flags to indicate zero-part locations for improved ECC reliability. This method also implements Hamming ECC code on the base die for effective error correction, ensuring the integrity of CRC bits to the host. Experimental results show that this approach achieves high reliability when zero parts are included in addressing errors that occurred in the memory die and through silicon vias (TSV) with low hardware overhead.
In this paper, we propose a mapping-aware weight pruning method for in-memory computing (IMC) architectures that operate on a row-by-row basis. Our proposed method can dynamically skip unnecessary row operations to minimize energy consumption while maintaining the inference accuracy of pre-trained model. To achieve this, it calculates the importance of weight elements considering the weight mapping method, which helps preserve critical weights in pre-trained model, thereby minimizing inference accuracy loss. The simulation results demonstrate that our method not only enhances scalability by allowing users to select the number of row operations to be skipped, but also achieves superior inference accuracy compared to existing pruning method in both ResNet-20 and WRN16-4 networks.
Botnet is one of the cyber security threats which may cause big damages. This research uses Machine Learning methods to classify and then detect botnet attacks. The CTU-13 dataset is used, and 90,962 records are trained in a 3-layer Deep Learning sequential model. The result has 99% accuracy and the value of recall, precision and F1 score is 99% as well.
Gridless Gap Channel Routing (GGCR) is a routing problem defined in a critical routing layer in an advanced chip where each net is connected by a single horizontal trunk Steiner tree. The trunk widths are not unique, and trunks are assigned to partitioned routing areas, called gaps, without overlap. In this paper, we propose Gap Swap-Flip (GSF) that reduces the total vertical wirelength of connections of nets. GSF is a greedy heuristic that modifies a given initial trunk assignment to reduce the total vertical wirelength and obtains near-optimal solutions efficiently.
This paper presents a methodology of the automated inductor generator for radio-frequency (RF) integrated circuit. We propose a machine learning assisted parameterized-cell (PCELL) generation method. This method supports polygonal, circular and asymmetric inductor shapes. The proposed PCELL has been validated in 65-nm CMOS 1P9M process and analyzed in terms of inductance (L), quality factor (Q factor) and area. An artificial-neural-network (ANN) based regression model is trained to reduce the EM based inductor design cost such as x530 less simulation time. According to the target inductor design optimization, 1 GHz operating frequency, we achieve the relative error rates of 0.63% and 1.73% for L and Q factor, respectively.
This paper presents a novel design technique for reducing ripple in various sensor read-out integrated circuits (IC) by calibrating the amplifier offset through current control in bias resistors. Traditional methods for reducing ripple often involve complex amplifiers consuming static power. In contrast, the proposed ripple reduction technique employs successive-approximation register (SAR) logic to control the current flowing through the bias resistor, thus minimizing static power consumption. Experimental results obtained through simulations in a 28 nm CMOS process demonstrate significant ripple reduction to 8.94.Vpp from 2 mVpp. This approach is suitable for low-power design, particularly in wearable device applications, and can potentially extend to other amplifier configurations utilizing chopping technique.
This paper presents an innovative All-Digital Phase Locked Loop (ADPLL) with a robust delay line configuration that enhances system resilience across changing environmental conditions. The proposed ADPLL integrates a pair of delay lines, called ping-pong delay lines, allowing a wide frequency tracking range without compromising the integrity of the loop operation. Under the VDD-changing scenario, which includes a voltage drop from 1V to 0.97V within 15 microseconds, the ADPLL demonstrated consistent performance, highlighting its potential for hostile operating conditions. The proposed ADPLL has an area of 0.04mm(2) and its output clock frequency ranges from 0.45GHz to 1.45GHz, consuming 3.49mW of power at 1GHz. With the prosed Ping-Pong scheme, we could achieve a 29.5% peak-to-peak jitter reduction when compared with our baseline ADPLL under a VDD-changing scenario in five corners, 25 degrees C.
