There are provided techniques for forming transistor architectures with extended recessed spacer and source / drain (S / D) regions. In some embodiments, a recess for example in the upper part of a ridge of a field effect transistor on Gratbasis (finFET) can be formed so that the recess enables the formation of extended recessed spacer and S / D regions in the finFET applied to the gate stack adjoin. In some instances, this configuration provides a greater resistance path in the upper part of the ridge, thus gate-induced drain leakage (GIDL) may be reduced in the finFET. In some embodiments, a precise adjustment of the onset of GIDL can be provided. Some embodiments may provide (V The disclosed techniques can be implemented on Gratbasis in some embodiments having planar and non-planar architectures and in conventional metal-oxide-semiconductor (MOS), and complementary MOS (CMOS) process sequences are used.