A leading edge 14 nm SoC platform technology based upon the 2 nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um 2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

An x86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.

The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cutoff frequency (f(T)) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.

A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an f(T) of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an fT of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High Q inductors, >7V breakdown voltage power amplifier transistors, varactors, and precision passives are also presented.

A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um2) and low voltage (0.171 um2) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum 2 , and on multiple microprocessors.

A 45nmlogic technology isdescribed that forthefirst time incorporates high-k ±metal gate transistors inahigh volume manufacturing process. Thetransistors feature 1.OnmBOT6 high-k gatedielectric, dualbandedgeworkfunction metal gates andthird generation strained silicon, resulting inthe highest drive currents yetreported forNMOS andPMOS. Thetechnology alsofeatures trench contact basedlocal routing, 9layers ofcopper interconnect withlow-k ILD,low cost193nmdrypatterning, and1000o Pb-free packaging. Process yield, performance andreliability aredemonstrated on153MbSRAM arrays withSRAM cell size of0.346gtm2, Fig. 2TEMofHigh-k +Metal Gatetransistor stack andonmultiple microprocessors.

RF CMOS performance from a 90nm derivative communications process technology is compared to SiGe BJT performance. NMOS performance at f/sub T//f/sub max/ = 209/248 GHz (70nm) and f/sub T//f/sub max/ = 166/277 GHz (80nm) with F/sub min/ at 0.3 dB (2GHz) and 0.6 dB (10GHz) suggests there is no major reason to implement SiGe HBTs BiCMOS in an integrated communications process.

This paper presents a highly-manufacturable process technology featuring SiGe HBT devices fully integrated into a 90 nm leading-edge high performance CMOS technology. The technology was developed on a 300 mm wafer platform, and supports process elements including RF CMOS devices, a MIM capacitor, precision resistors, high-Q inductors and varactors.

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage, It is shown that V-th roll-off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off state currents Less than 5 x 10(-12) A/mu m and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V, poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths.