Large-scale optical switch networks employ wavelength division multiplexing to expand and facilitate multiple input and outputs. Such networks can be implemented with the Mach-Zehnder interferometer (MZI) as the building block. A fully-loaded MZI switch, meaning one with two optical signals at its two inputs and one that is capable of simultaneously switching those inputs to its two outputs, reduces the number building blocks within the network, and as a result makes them more power and area efficient. However, for practical operation, such MZI switches need to be automatically controlled for overcoming fabrication and thermal variations. We present an interference-based monitoring method that enables automatically switching, tuning, and stabilizing of a fully-loaded 2×2 MZI optical switch and demonstrate a prototype on an SOI platform. Using the proposed device and off-the-shelf electronics, we demonstrate automatic tuning and stabilization of an MZI switch with 12.5 Gb/s and 25 Gb/s data rates and channel spacing as small as 1 nm.

A silicon photonic TE-pass polarizer is demonstrated using serpentine 180° adiabatic bends, in an MPW foundry process. By choosing the number of bends, a designer can trade TM extinction versus TE loss. 16 dB extinction had 0.37 dB loss. 26 dB extinction had 0.78 dB loss.

Silicon waveguide crossings using multi-mode interferometers are highly sensitive to geometry at the internal corners. Optical proximity correction was developed using design-of-experiments without sophisticated foundry modeling. This simple technique improved loss by a factor of 2, to <30 mdB, while maintaining flatness over C-band.

We demonstrate experimentally a fundamentally new low-loss silicon nanophotonic in-plane crossing. The crossing operation uses a three-mode synthesis of a 1-D Gaussian beam. The measured loss is 0.007 dB ± 0.004 dB, which is the lowest reported loss for silicon waveguide crossings.

ESD sensitivity of silicon photonics critically affects manufacturability. We report the ESD sensitivity of monolithic silicon photonic elements, using ESDA/JEDEC tests. TiN heaters were class 1C, requiring JEDEC Basic ESD Control. Ge-photodiodes were class 0B, requiring Detailed ESD Control, unless on-chip ESD solutions are implemented.

Experimental results of 1×2 and 2×2 carrier-injection Mach-Zehnder switch cells fabricated on a commercial multi-project wafer are reported. The performance of the devices is compared to targets determined by system architecture.

This paper reports experimental results on compact, low-loss and broadband optical waveguide crossing structures fabricated in a CMOS-compatible process. Insertion loss of 0.11 dB/crossing and crosstalk below -45 dB are achieved in devices with 6.5 × 6.5 μm2 footprint.

We demonstrate photonically-assisted generation of RF arbitrary waveforms using planar lightwave circuits (PLCs) fabricated on silica-on-silicon. We exploit thermo-optic effects in silica in order to tune the response of the PLC and hence reconfigure the generated waveform. We demonstrate the generation of pulse trains at 40GHz and 80GHz with flat-top, Gaussian, and apodized profiles. These results demonstrate the potential for RF arbitrary waveform generation using chip-scale photonic solutions.

Optical waveguide crossings based on silica-on-silicon technology are investigated. The effect of crossing angle (θ) on light transmitted at through and cross-port on a sequence of waveguide crossings with angle varying from 7 to 28° is modeled and experimentally validated. Results demonstrate that structures with small footprint (θ≈9°) can achieve low crosstalk of -32 dB with high throughput, insensitivity to wavelength of operation, low polarization dependent loss of 0.6 dB, and low sensitivity to fabrication tolerances. As a result, waveguide crossings with small crossing angle present an attractive approach to reducing the overall component footprint without compromising the performance.

We demonstrate photonically-assisted generation of arbitrary RF waveforms with a bandwidth from 20 - 80 GHz using a reconfigurable silica-based planar lightwave circuit.

A new interferometer-based optical sensing platform with nanostructured thin films of ZrO2 or TiO2 as sensing environment has been developed. With the application of an IC compatible Si(3)N(4) waveguide technology, Mach-Zehnder interferometer devices have been fabricated. The application of the glancing angle deposition technique allowed fabrication of nanostructured thin films as the optical sensing environment. Sensing ability of fabricated devices has been demonstrated through the refractive index measurement of a known gas. The transmission spectra and time response measurements have demonstrated a maximum phase shift of Delta phi=pi/10 and a |Delta P(out)|=0.65 dBm. Devices with TiO2 film on the sensing region performed much better than devices with ZrO2, with sensitivity twice as high.

Highly selective and anisotropic low temperature electron cyclotron resonance plasma etching process for silicon nitride optical rib waveguide devices compatible with integrated circuit technology is presented. Etching at low temperatures (−30°C) with SF6∕O2 chemistry in combination with a silicon dioxide hard mask achieved good anisotropy with the vertical sidewalls.

An algorithmic technique is presented that allows estimation of maximum temperature rise in a thermal model with component-board thermal interaction. The technique is based on a generalized thermal port grouping to estimate the interface temperature profile derived from coarse port assignments. By using a very simple environment, it takes a library-type thermal component model with many thermal ports included and transforms it by grouping thermal ports based on a temperature profile, allowing a minimal number of port groups to provide the same accuracy as the original model in a shorter time. The usefulness of this technique is illustrated through simulation of two thermal models with extreme nonuniform temperature distribution on the interface surface. The prediction accuracy is evaluated by comparison with the final solutions to numerical simulation.

A novel approach of a first order optimization technique applicable to design process of photonic sensing devices and waveguide geometries is presented. The application of the optical field sensitivity mapping technique enables first order optimization of geometrical parameters with the final goal of enhancing the overall device sensitivity. The technique is simple, requiring only two simulations of optical field propagation and the extraction of a sensitivity map. The method is demonstrated in a design optimization process of a realistic multi mode interference sensing device. As a result, optimization of the MMI active section length, sensing region width, and the output location was accomplished. A comparison between the optimized device and two other ones of different length showed a 10 dB higher dynamic range of the output power ratio characteristic and better linearity, demonstrating enhanced sensitivity of the final device.

In this paper, a generalized method for the connection of a thermal component model in board- and system-level thermal simulations is presented. The method allows for the definition of uniform heat flow connections as well as the standard uniform temperature interface regions. The use of uniform heat flow ports will be shown to better handle cases where large temperature gradients are present in the base model. The two methods of connecting the component model will be evaluated using two different models. First, a simple example will be presented to illustrate the nonphysical behavior introduced by the use of uniform temperature connections. Second, a model of an electronic package will be used to evaluate the relative merits of the two connection methods with respect to board thermal conductivity and boundary conditions present on the board and the package. It will be shown that the results from use of uniform heat flow connections are generally better than from use of uniform temperature regions with respect to predicting junction and board temperatures.

This paper presents a new approach to compact thermal modeling. The paper shows how a parameterized reduced thermal model of an IC component can be created based on a parametric model reduction technique. By applying this technique, a large system of equations characterizing a discretized fully detailed numerical thermal model can be drastically reduced. The final product of a parameterized model reduction procedure is a set of small matrices presenting an abstract description of the component thermal behavior. The reduced system can be used to either synthesize a resistive network or formulate a set of connection equations to be connected to higher simulation levels. External boundary conditions are parameters of the reduced model and can be specified at simulation time. A parameterized reduced thermal model is found to have a number of advantages over an optimized resistor network model. The model can be generated quickly (one lower-upper (LU) decomposition is needed), high accuracies are obtained with a typical error of less than 0.1%. The technique also predicts temperature at all internal nodes of the original detailed model not just a single junction temperature. In this paper, the new technique is demonstrated through two examples of realistic IC components: a GaAs power amplifier and a generic multichip module ball grid array package. Both reduced models are connected to substrates in a number of different configurations. Thermal analysis performed in each case shows the importance of the geometric configuration of the connections on predictive capability.

This paper presents a new approach to hierarchical thermal modeling using libraries of parametrized sub-models. It is demonstrated how to efficiently create thermal sub-models based on a parametrized model reduction technique. These sub-models are then used for fast simulation of complex parts using a hierarchical modeling building methodology that nests sub-models within sub-models. As an example of such a model parametrized thermal sub-models of a GaAs power cell, an integrated GaAs microwave power amplifier and an InP optical modulator are generated. A complete module is then built by attaching these sub-models to detailed models in a hierarchical manner, creating a thermal model of the entire system. This methodology allows a quick thermal analysis to be performed of very large systems. The thermal sub-models are small in size, boundary condition independent, have very short simulation times, and predict with high accuracy (better then 2% error) all internal temperatures. Finally, the optical modulator model is used as example of the computational efficiency of the methodology. Although an absolute speed-up is difficult to define two cases were provided with gains of around 30 to 40 times calculated. System memory requirements were also reduced by a factor of three.

In this paper, a model reduction technique is applied to the thermal modeling of electronic components and devices with complex geometries. The reduced-order model is capable of predicting a complete detailed three-dimensional temperature distribution in the original model. The small size and the simplicity of the reduced model allows for the very quick simulation of the device under a wide range of input parameters, such as different boundary conditions and power distributions. Use of the reduced-order model in a thermal design cycle can have a significant effect on both prediction accuracy and simulation efficiency. In the paper, the usefulness of this technique is demonstrated through examples from different electronic devices and packages. Accuracy of the reduced-order model is validated by comparison with the solution to a detailed numerical model.

This paper presents a new approach to thermal modeling using sub-models. We show how to efficiently create thermal sub-models based on a multi dimensional model reduction technique. These sub-models are then used to allow for fast simulation of complex parts and build higher order sub-models. In the paper multi dimensional thermal sub-models of realistic IC components such as an MMIC power amplifier for a fiber optic transmitter system and a generic multi-chip module ball grid array package are generated. Each sub-model is attached to a base detailed model such as a PCB or substrate, creating a thermal model of the entire system, allowing a quick thermal analysis to be performed of large systems. The thermal sub-models presented demonstrate a small model size, short simulation time, and high accuracy in the prediction of all internal temperatures with an error less than 2.5%.

A compact I x 2 waveguide digital optical switch (DOS) with electrically reconfigurable output waveguide arms is proposed and demonstrated. Calculations show that this switch can be much shorter and consume less power than previous DOS designs. An InGaAsP-InP waveguide device based on carrier injection was designed and fabricated and exhibits a 20-dB switching contrast ratio. The device length is 1400 mum.