The need for flexible interconnects in advanced applications in consumer electronic products is increasing rapidly. The reliability and flexibility of ultra-thin chip-on-flex (UTCOF) interconnects formed using anisotropic conductive adhesive (ACA) are thus investigated. Two films of ACA materials, namely ACA-P and ACA-F, are assembled at different bonding temperatures to study the effect of temperature on the adhesion at the substrate-adhesive and adhesive-chip interfaces using differential scanning calorimetry (DSC) and a 90° peeling test. The contact resistance of a daisy chain with 188 input/output (I/O) is measured to examine the quality of bonding through dummy test samples with an 80-μm pitch. The reliability of the fabricated UTCOF interconnects bonded via selected ACA joints is evaluated by performing an 85°C/85% RH thermal humidity storage test (THST) for 1000 h, and their flexibility is evaluated in static bending and four-point bending tests. The interfaces between the ultra-thin silicon chip and the substrate of failed samples in the THST and four-point bending testing are then investigated by scanning electron microscopy (SEM), which is utilized to obtain cross-sectional images. Finite element analysis is also conducted to elucidate the failure mechanism of the UTCOF interconnects in the four-point bending test. The averaged maximum allowable deflections of the fabricated UTCOF interconnects with ACA-P and ACA-F materials are 26% and 168%, respectively, higher than those of the COF interconnects with a chip thickness of 670 μm. Moreover, the contact resistance remains stable, varying by less than 10%, in the static bending test with a bending radius of 30 mm. According to the results thus obtained, give the appropriate choice of an ACA material and the optimal curing conditions, the UTCOF interconnects with ACA joints reliably serve as flexible interconnects for use in consumer electronic products.
This paper presents the design and development of a compact 3-D transmit/receive (T/R) module with a selectively anodized aluminum multilayer package for X-band phased array radar applications. The proposed multilayer package consists of anodized aluminum substrates and vertical interconnects with embedded vias. The proposed package platform is based on thick anodized aluminum oxide layers and active bare chips directly mounted on bulk aluminum substrates for high electrical isolation and an effective heat sink. With its combination of thin-film embedded passive components and multilayer structure, the proposed module features a compact size of 20 mm × 20 mm, with a package height of 3.7 mm. To transfer radio-frequency (RF) signals vertically, we used coaxial hermetic seal vias with characteristic 50 Ω impedances and embedded anodized aluminum vias with a solder ball attachment and flip-chip bonding. The optimized vertical interconnect structure demonstrates RF characteristics with an insertion loss of less than 1.55 dB and a return loss of less than 12.25 dB over a broad bandwidth ranging from 0.1 to 10 GHz. The fabricated X-band 3-D T/R module has a maximum transmit output power of 39.81 dBm (9.5 W), a maximum transmit gain of 41.25 dB, and a receive gain of 19.15 dB over the 9-10 GHz frequency band. The RF-signal phase amplitude control is achieved by means of a 6 bit phase shifter with an rms accuracy of more than 5° and a gain setting range of 24 dB with an rms accuracy of more than 1.5 dB. The proposed multilayer aluminum package has the advantages of reducing the module size, decreasing the cost, and managing the thermal problem for X-band high-power T/R module package applications.
This paper presents, for the first time, characterization results of next generation dielectric core and build up material called RXP, which has low dielectric constant (2.93-3.48) and low loss tangent (0.0037-0.006) up to 110 GHz. Unlike LCP, this material can be made ultra-thin with low processing temperature and is ideally suited for mobile applications. Causal models suitable for high frequency applications have been extracted by measuring the response of cavity resonators using vector network analyzer and surface profiler.
A low-cost test method is proposed for testing integrated radio-frequency (RF) substrates with embedded RF passive filters. The proposed method enables the testing of embedded high-frequency gigahertz filters by the analysis of low-frequency signal of the order of 100 MHz. In addition, the test method allows the testing without injecting external test stimulus into RF filters. Hence, significant reduction in the test cost is achieved by the proposed test method. As compared to the conventional test method which uses vector network analyzer (VNA), the proposed method reduces the test-setup cost by around 75%. The proposed test method relies on three core principles. First, the RF filter is made a part of the feedback network of an external RF amplifier circuit located on the probe card, thereby causing the amplifier to oscillate. Second, the output spectrum of the amplifier (GHz) is down-converted to a lower frequency (MHz) to facilitate test response measurement. Third, RF (GHz) specifications of the filters are predicted by the analysis of the low-frequency (MHz) test-setup output. Both parametric and catastrophic failures in the embedded high-frequency (GHz) passive filter can be detected at low-frequency (MHz) by monitoring the change in the oscillation frequency of the proposed test setup. The test method is demonstrated with both simulations and measurements.
A new concept of compromise impedance match design is proposed for pogo pins with various signal-ground patterns. To begin with, the methodologies of equivalent circuit modeling for single-ended and differential pogo pins are described. A de-embedding technique is proposed to eliminate the effect of a specialized test fixture for the characterization of the pogo pins. Good agreement is found from the comparison between measured and simulated results, which validates the modeling and simulation methodologies. Then, the reflection of pogo pins with various signal-ground patterns is investigated and the optimal pin radius to pitch ratio is found to be 0.20-0.21, thereby achieving a return loss better than 15 dB for all these patterns in both single-ended and differential configurations from dc to 10 GHz. In addition, the effects of pin length are considered and a general design chart is constructed for determining the pogo pin geometry and the applicable impedance range to meet the specification on the return loss. Several compromise impedance design applications demonstrating the proposed methods are given.
Chip stacking with through-silicon-vias (TSV) technology for 3-D packaging of electronic devices was investigated. A new process of direct solder bumping on Si wafers without photoresist (PR) mould was designed and applied in this study. The Cu extrusion process on the via was also omitted for process simplification. This simplified process can be useful for cost reduction and increased productivity. The substrate for the experiments was a p-type 〈100 〉 Si wafer of 100 mm diameter. In order to produce the vias, the Si wafer was etched by a deep reactive ion etcher (DRIE) using SF6 and C4F8 plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO2, Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm2 and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm2 and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm2. The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by micro-soldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu6Sn5 intermetallic compound was pr- - oduced with a thickness of 3.2 μm. Through this study, a process for non-PR solder bumping by electroplating and wafer stacking with TSV was achieved successfully.
In this paper, an embedded electromagnetic bandgap structure is proposed for harmonic filtering of differential signal's undesired common mode components. Rather than use lumped circuit components and likely causing some degradation to the intended high speed differential signal, the embedded planar common mode filter causes no degradation to the intended signal, and enhances the signal integrity and electromagnetic compatibility performance of the system. Single ended and differential traces are considered and the impact of the common mode filtering is measured in terms of mixed mode scattering parameters and eye diagram metrics. The systematic procedure to design such a structure is outlined, and its design robustness is also verified.
In this paper, we present a comprehensive equivalent circuit model to accurately characterize an important class of electromagnetic bandgap (EBG) structures over a wide range of frequencies. The model is developed based on a combination of lumped elements and transmission lines. The model presented here predicts with high degree of accuracy the dispersion diagram over a wide band of frequencies. Since the circuit model can be simulated using SPICE-like simulation tools, optimization of EBG structures to meet specific engineering criteria can be performed with high efficiency, thus saving significant computation time and memory resources. The model was validated by comparison to full-wave simulation results.
The paper shows the importance of nano-roughening on the bonding interface to the reliability enhancement of adhesive bond for ensuring the continuation of packaging shrinkage from MEMS to NEMS. The roughening is realized via a nonuniformly etching characteristic of PR which is etched and then utilized as an etching mask for following silicon etching process. Ultraviolet adhesive for silicon-to-glass bonding is utilized for the verification of the nano-roughening effect on NEMS hermetic encapsulation. The average roughnesses of the silicon substrate before and after roughening are 0.4 nm and 12.4 nm, respectively. Experimental results show that the roughness increase of silicon substrate can effectively provide more than 30% bonding strength enhancement and 30% leakage reduction. In addition, stamp-and-stick test shows that nano-roughening indeed provides a better adhesive characteristic that can further ensure the success of the stamp-and-stick process for nano/microfabrication.
Through-silicon-via (TSV) interconnects using the "via-last" approach are successfully applied for wafer-level packaging of complementary metal-oxide-semiconductor (CMOS) image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening, and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer-level packaging process for optical and M(O)EMS devices.
Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.
Stretchable interconnects play an important role towards the realization of the realm of systems that include large-area sensor skins and wearable electronics. These interconnects must be reliable and robust for viability, and must be flexible, stretchable, and conformable to nonplanar surfaces for diverse applicability. This research describes the design, modeling, fabrication, and testing of stretchable interconnects on polymer substrates using metal patterns both as functional interconnect layers and as in situ masks for excimer laser photoablation. The fluences for photoablation of polymers are generally much lower than the threshold fluence for removal or damage of metals; thus, metal thin films that are designed as structural layers in the sensor skin can be used as in situ masks for polymers if the proper fluence is used. Self-aligned single-layer and multilayer interconnects of various designs (rectilinear and “meandering”) have been fabricated, and certain “meandering” interconnect designs can be stretched up to 50% uniaxially while maintaining good electrical conductivity and structural integrity. Furthermore, redundant interconnect meshes have been modeled and fabricated that increase the viability of the interconnect mesh while stretching up to 30% uniaxially and a prototype redundant interconnect mesh has been fabricated using seamless-scanning large-area fabrication techniques.
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulated, and filled with copper employing a bottom-up copper electroplating technique in a “via-first” approach. DC via resistance measurements show good agreement with the theoretical expected value (~ 16 mΩ) . Radio-frequency (RF) measurements up to 50 GHz have been performed on coplanar waveguides located on the back-side of the wafers and connected to the front-side with TSVs. The S-parameters indicate clearly the beneficial impact of double sided ground planes of the RF signals. The via resistance extracted from impedance measurements is in good agreement with dc values, while the inductance (53 pH) and capacitance (2.4 pF) of the TSV are much lower than conventional wire bonding, which makes the use of TSV very promising for 3D integration. An advanced analytical model is proposed for the interconnect system with vias and lines and shows very good agreement with the experimental data with a limited number of fitting parameters. This work gives a proof of concept for high aspect ratio TSV manufacturing and new insights to improve 3D interconnect modeling for systems-in-package applications in the microwave regime.
In this work, a CO2 laser-assisted silicon lid sealing process, utilizing Au80/Sn20 solder, for encapsulating gas breakdown test micro-electro-mechanical structures (MEMS) in a ceramic quad flatpack (CQFP) was studied. Wire bonded MEMS dies were sealed into CQFPs under various gas media, such as air, nitrogen, helium and vacuum. The gas breakdown test results showed a significantly higher breakdown voltage for vacuum packaged parts compared to those packaged in other various gas environments. Hermeticity testing according to MIL-STD-883E showed that the leak rate of the package was below 10-8 atm cc/s. The bonding was uniform and the bonding strength is believed to be comparable to the tensile strength of Au80/Sn20 solder.
With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models.
Multistacked-chip scale package (S-CSP) is a new technology that provides high density electronic package. A fully 3-D numerical model is developed to simulate mould filling behavior in the epoxy moulding compound (EMC) encapsulation of multi-S-CSP. Four different shapes of chip arrangement namely uniform, rotated, z-staggered-Type A and z-staggered-Type B, have been tested. The EMC is treated as a generalized Newtonian fluid (GNF). The developed methodology combines the Kawamura and Kuwahara technique-based finite difference method (FDM) and the robustness of volume-tracking (VOF) method to solve the two-phase flow field around the complex arrangement of microchips in a cavity. The Castro-Macosko rheology model with Arrhenius temperature dependence is adopted in the viscosity model. Short-shot experiments are conducted to investigate the filling patterns at several time intervals. The results show that the rotated shape die-arrangement gives minimum filling time and better mould filling yield. The close agreement between the experimental and simulation results illustrates the applicability of the proposed numerical model.
This paper proposes an efficient method to model through-silicon via (TSV) interconnections, an essential building block for the realization of silicon-based 3-D systems. The proposed method results in equivalent network parameters that include the combined effect of conductor, insulator, and silicon substrate. Although the modeling method is based on solving Maxwell's equation in integral form, the method uses a small number of global modal basis functions and can be much faster than discretization-based integral-equation methods. Through comparison with 3-D full-wave simulations, this paper validates the accuracy and the efficiency of the proposed modeling method.
A novel electromagnetic bandgap (EBG) structure is proposed for broadband suppression of gigahertz simultaneous switching noise. The structure is composed of three-dimensional interdigital capacitors (3D-IDC) and series U-shaped transmission lines periodically. The EBG structure can be miniaturized based on the LTCC fabrication technology. A theoretical circuit model which considers the inductive coupling in the 3D-IDC will be developed to predict the stopband. The accuracy of the proposed model will be verified by comparing with both the full-wave simulation and the measurement results. This modeling method is also employed to study the variation of bandgap dependent on different geometrical parameters for the 3D-IDC and the U-shaped transmission line. A prototype is implemented using the LTCC technology with the dimension 1.2 mm × 3.8 mm × 0.728 mm. Both simulation and measurement show the rejection band is from 2 to 5.5 GHz. Over 45 dB noise reduction in the stop band could be achieved. In addition, the suppressive ability is also verified in the chip-package co-simulation. From the simulation result, significant reduction of power noise could be found both in digital and mixed signal circuits.
In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and occupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and measurement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer.
