The types of detectors and the physics involved in present experiments are reaching a level of cost and complexity so great that it is preferable to implement a programmable trigger solution at all levels rather than a system realized with cabled logic. Experience demonstrates that fine tuning on the trigger is often achieved only after running an experiment and analyzing the first data acquired. A level-1 trigger is required to identify objects (particles such as electrons, jets, etc.) with programmable algorithms at 60 million frames-per-second. These requirements have led to the design of a special 3-D flow processor that, together with a special pipelined parallel-processing architecture, allows a sustained data rate of 60 million frames-per-second. The 3-D flow is a data-flow processor that can be used in one-, two-, or three-dimension arrays for high-speed signal-processing applications such as identifying objects in a matrix in a programmable form. Feasibility studies demonstrate that with present technology a 3-D flow chip consuming 8 W and accommodating 32 processors at 60 MHz can be built today, and that the same chip can be built one year from now at a 120-MHz clock rate

The STAR experiment reads out a TPC (Time Projection Chamber) and an SVT (Silicon Vertex Tracker), both of which require on-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. We describe the design and implementation of the ASIC, as well as testing methodology and results of tests performed on foundry prototypes.

STAR is a large TPC-based experiment at RHIC, the relativistic heavy ion collider at Brookhaven National Laboratory. The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. The authors describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

The LHC-B collaboration is in the process of designing a forward spectrometer, optimized for the detection of Beauty particles, to run at the LHC collider. One very crucial aspect of the design is the global multi-level trigger scheme, required to reduce the event rate from around 40 MHz (the LHC beam crossing rate) down to the foreseen recording rate of a few KHz.At Level-1, it is currently envisaged to implement high p(t) electron, muon and hadron triggers. The requirements for Level 1 are to accept, with zero deadtime, events at the 40 MHz rate, and to provide an answer within a couple of microseconds. The rejection rate for minimum bias events expected of Level 1 is of the order of one hundred.The 3D-Flow system can implement the above requirements in real time with zero dead-time giving the user the flexibility to change at later time the algorithm, including more signals in the decision process, and to upgrade incrementally the system with changes in granularity and/or segmentation.

The applicability of the 3D-Flow system to different experimental setups for real-time applications in the range of hundreds of nanoseconds is described. The results of the simulation of several real-time applications using the 3D-Flow demonstrate the advantages of a simple architecture that carries out operations in a balanced manner using regular connections and exceptionally few replicated components compared to conventional microprocessors. Diverse applications can be found that will benefit from this approach: High Energy Physics (HEP), which typically requires discerning patterns from thousands of accelerator particle collision signals up to 40 Mhz input data rate; Medical Imaging, that requires interactive tools for studying fast occurring biological processes; processing output from high-rate CCD cameras in commercial applications, such as quality control in manufacturing; data compression; speech and character recognition; automatic automobile guidance, and other applications. The 3D-Flow system was conceived for experiments at the Superconducting Super Collider (SSC). It was adopted by the Gamma Electron and Muon (GEM) experiment that was to be used for particle identification. The target of the 3D-Flow system was real-time pattern recognition at 100 million frames/sec.

Recent years have witnessed a growing interest in the study of neural networks. A lot of work has been on understanding how various computational problems can be solved adopting these models. This paper describes an asynchronous feedback neural network, the photon event identification problem in an astrophysics experiment, and shows some promising results.< >

This report describes an implementation on the 3D-flow system developed at the Superconducting Super Collider Lab. of the algorithms and equipment to recognize valid photon events using a morphological analysis of the signals of an intensified CCD in the photon counting mode. The analysis consists of calculating the coordinates of a matrix corresponding to the exact position of each incident photon on the channel plate. Several off-line calculations with efficiency studies aiming at finding the best algorithm for event reconstruction have been performed. This off-line algorithm can be accomplished in real time at the CCD input rate (up to 2000 frames/sec). The communication-intensive nature of the algorithm and of the topology of this application and the particular architecture of the 3D-flow system lead to a very efficient implementation. The existing hardware simulator allows studies of the entire system before actual construction.< >

The advent of powerful microprocessors that surpass our number-crunching requirements has not relieved the need of HEP experimenters to design and build ASICs for front-end and triggering applications, because a simpler and specialized circuit is still required. One such circuit is the 3D-Flow processor. Better described as an architecture rather than merely an ASIC, the 3D-Flow allows the user to build a programmable Level-1 trigger, and it is also suitable to be used in data acquisition (DAQ), data movement, pattern recognition, data coding and reduction. Test vectors, including several Level-1 trigger and DAQ algorithms, have been generated for the 3D-Flow ASIC. Pattern recognition algorithms for a calorimeter take less than 500 ns to execute. The system also implements sophisticated tracking and track-matching algorithms, and can execute thousands of steps in Single Instruction Multiple Data (SIMD) mode. The high degree of connectivity between processors, and their multiple operation execution capabilities, is an especially significant advantage with respect to other systems. As has been substantiated (see discussion below) at present the 3D-Flow system is the only detailed study demonstrating the feasibility of executing several Level-1 trigger and data reduction algorithms of different experiments.

The 3D-Flow is a massively parallel-processing system. Its main advantages are embodied in its architecture: the system (integrated and standardized), the assembly (modular with maximum connectivity), and the processor (programmable, powerful and fast). The combination of this architecture with a simple, high-speed processor that has several units working in parallel, with its 10 very-high-speed communication parallel ports in six directions, and the ability to operate the processor in Single Instruction Multiple Data (SIMD), or in Multiple Instruction Multiple Data (MIMD) modes, allows one to build a very versatile engine. This engine is capable of solving at very high speed with a very high degree of interconnectivity a very long algorithm (in SIMD mode), or it can perform digital filtering on high-frequency signals or pattern recognition in a very short time, using a short algorithm that can be different on each processor (in MIMD mode). The overall 3D-Flow project has passed a major design review at Fermilab. (Reviewers included experts in computers, triggering, system assembly, and electronics.)

The types of detectors and the physics involved in present experiments are reaching a level of cost and complexity so great that it is preferable to implement a programmable trigger solution at all levels rather than a system realized with cabled logic. Experience demonstrates that the fine tuning on the trigger is often only achieved after running an experiment and analyzing the first data acquired. Recent advances in technology made real-time programmable algorithms down to the Level 1 trigger feasible. In this report a number of algorithms for the first level trigger have been simulated using one of the most advanced chips available. A fully-pipelined and programmable Level 1 trigger system sustaining a clock rate of 16 ns has been designed based on a modified version of the DataWave chip. gem

A proposal for a parallel-processing system based on data-driven array processors, digital signal processors and Transputers for trigger decision, data acquisition (DAQ) and compaction will be presented. The system is modular and suitable for any calorimeter size and type such as the ones proposed in the R&D for the LHC and SSC experiments. The aim is to give full programmability for trigger decisions and for the data compaction, over the entire calorimeter at the single-channel granularity level, with no boundary limitation. The present project is an example of the efficient integration of commercial components into the front-end electronics of future detectors for high energy physics (HEP), in place of developing new VLSI processors for this special purpose application.

A feasibility study has been made to use the 3D-Flow processor in a pipelined programmable parallel processing architecture to identify particles such as electrons, jets, muons, etc., in high-energy physics experiments.

DELPHI is a 4-pi detector with emphasis on particle identification, three-dimensional information, high granularity and precise vertex determination. The design criteria, the construction of the detector and the performance during the first year of operation at the large electron positron collider (LEP) at CERN are described.