Direct waferbonding is an appropriate technology to join two or more wafers of the same or of different materials. Waferbonding can be used to stiffen thin wafers during fabrication. However, conventional fabrication processes lead to an increase of the bond strength, which inhibits the required de-bonding. The propagation of cracks, which is based on a subcritical crack growth in the bonded interface, was used to cleave the bonded wafers. The subcritical crack growth is limited to the bonded interface, since the adjacent bulk semiconductor materials are inherently resistant to subcritical crack growth. The process allows the separation of Si-Si and Si-GaAs wafers after annealing. Wafer-bonded SOI wafers can also be separated with this technology even if they were annealed at 1100°C. The first examples for wafer stiffening during fabrication and wafer transfer using the developed approach will be presented.

The detection limit of infrared thermographic investigations can be improved down to 10 μK by using a highly sensitive high-speed infrared camera in an on-line averaging lock-in thermography system. Together with a microscope objective, this allows lock-in thermography to be used as a simple and sensitive technique to localize the sites of leakage currents and other heat sources in electronic components. The practical realization of a novel lock-in thermography system is described and both test measurements and practical applications are introduced. The detection limit for surface-near local heat sources in silicon is a few microwatts with a spatial resolution down to 5 μm. Leakage sites in several microelectronic structures are imaged and assigned to the layout of the integrated circuit by comparing direct images with lock-in ones. The direct comparison of an averaged and background-subtracted stationary thermogram with a lock-in one, both measured under similar conditions at the same sample, clearly demonstrates the gain in information obtained by using lock-in thermography.

Using indentation testing, wire bond tests and electron microscopy, the influence of increased oxide films on Al metallization surfaces on the wire bonding behavior and hardness was investigated. Oxide film thickness values larger than about 20 nm obstruct the bond contact and resulted in a poor bonding quality. The presence of such films causes also a hardness increase which can be detected by current sensitive indentation test methods. Therefore, an improved indentation testing technique can be applied during the quality control of bondpad metallizations prior to wire bonding.

The pore geometry of nanoporous aluminum oxide membranes which were prepared by anodization of aluminum in polyprotic acids were observed using focused ion beam technology (FIB) and high resolution scanning electron microscopy (SEM). For demonstration of the columnar structure of the nanopores, depth profiles were prepared with the FIB technology. Based on the detailed information about the pore geometry, the inner surfaces of the pores were calculated.

Strength tests and fracture mechanics models for Silicon wafer-bonded components are presented which can be applied during the development of bonding technologies, for the yield improvement and failure analysis] as well as for the reliability assessment of micromechanical sensors and actuators. Special attention is given to the influences of atomic bonding strength, the interface voids and the notches caused by etching steps prior to bonding on the fracture limit. If wafer-bonded interfaces are exposed to a mechanical loading for an extended time, e.g. in the order of months or years, stress corrosion effects decrease the bonding strength. As a consequence, stressed sensors and actuators fabricated by wafer bonding can suddenly fail during application after a load-dependent lifetime. Based on an appropriate fracture mechanics model, the time-to-failure data could be theoretically predicted.

A procedure is presented of the cross-sectional preparation of locally well-defined areas in flip-chip packaged IC structures. Using mechanical and ion milling techniques, the silicon substrates are thinned from their bottom to optical transparency to observe the layer stack structure without damaging the active substrate areas. The IC layout is compared to optical images of the IC structures, which are taken of the downside of the chip. These images are used for the precise positioning during the cross-sectional preparation by means of the wire saw and the focused ion beam technique (FIB). The combination of conventional preparation techniques with optical microscopy and ion milling enables the preparation of transistor structures, conducting path 2, conducting holes as well as bonded interconnections in marked positions from the downside of ICs and their investigation by scanning (SEM) and transmission electron microscopy (TEM).

The influence of sharp notches in the interface of directly bonded components, of the oxide layer thickness and of the annealing temperature on the tensile strength of bonded samples was investigated. The critical notch intensity factor A(IC) was calculated from the fracture stresses using Finite Element Method (FEM) simulations. In contrast to fracture stress, Ale is a material property, that characterizes the atomic bond strength in the interface. Thus, determinations of A(IC) can be used to investigate the influence of bonding conditions on the bond strength, to study the homogeneity of strength properties and to predict theoretically the fracture limit of different anisotropically etched micromechanical wafer-bonded components.

Grain growth is studied during the thermal treatment of thin aluminium alloy layers on oxidised silicon substrates by means of transmission electron microscopy. The grain-specific texture of annealed layers is determined on-line by the Kikuchi pattern method. Elastic coefficients such as stresses and strains in reference directions in the layer, elastic energy and resolved shear stress on the glide planes are calculated in a first approximation on the basis of a biaxial stress model and a biaxial strain model considering measured grain orientations. The mechanisms of stress relaxation, some driving forces, and the effects on grain growth are discussed. Local inhomogeneities, particularly of the resolved shear stress, have an effect on grain growth. The conclusion is drawn that changes of grain orientation enable a preferential relaxation of stress by dislocation glide during grain growth. The results are illustrated by grey-level maps of the grain structure.

Stress-induced grain and hillock growth occuring in aluminium thin films thermally treated on their SiO2/Si substrates has been studied by in situ transmission electron microscopy (in planar and cross-section geometry) and by electron microscope surface techniques. The mechanical stress has been measured by a cantilever method. The grains, having a (111) texture after their deposition, have been observed to grow preferentially in the direction normal to the film surface. The grain size depends on the temperature-time regime applied: at temperatures higher than 400 °C, enhancing the temperature in a stepwise mode results in grains larger than after isothermal heating. This is attributed to different contributions of the main processes of stress relaxation involved. In the stepwise mode it is grain boundary diffusion that should prevail, whereas in the isothermal mode it is dislocation glide. Two processes of grain boundary movement can be distinguished: a stepwise shift and an instantaneous coalescence. The hillocks are formed in the range between 130 and 300 °C. Their growth is attributed to stress-induced grain boundary diffusion.