A plating sequence of the passivated emitter and rear cell (PERC) concept with Ni/Cu/Ag plated contacts which includes boron-oxygen (BO) defect regeneration and contact annealing is required to ensure a high and light stable efficiency accompanied by a low contact resistance. We introduce an inline-capable process of boronoxygen (BO) defect regeneration with a simultaneous annealing of the Ni/Cu/Ag plated contact within 10 seconds or less. As basis for the development of the inline capable process a transfer line method (TLM) test structure was used to identify process parameters with respect to time scale, temperature and illumination density. The experimental results demonstrate that an optimized process for simultaneous contact annealing and BO regeneration can achieve a full contact anneal after 1 second and an almost complete BO regeneration after 10 seconds. At higher temperatures above 500 °C a possible shunting through the emitter occurs along with no BO regeneration. Whereas lower temperature of 100 °C slows down contact annealing and BO regeneration significantly to a non-inline practicable process time. Hence, a good process window for complete BO regeneration and contact annealing was observed at a temperature of 250 °C with an illumination density of 27 kW/m2. Subsequently, the combined process was successfully transferred to an inline capable tool, which enables a significant speed-up of the contact annealing with simultaneous high BO regeneration. Furthermore, a smaller footprint, no need of nitrogen-rich atmosphere and reduced energy consumption are possible advantages compared to an inline thermal treatment oven for contact annealing.

Three approaches to close the efficiency gap between screen-printed Ag-paste and Ni/Cu/Ag-plated front contact metallization on industrial passivated emitter and rear cells (PERC) solar cells are presented in this paper. In the first approach, the POCl3 diffusion is adjusted to an emitter profile (reduced peak doping) for plated contacts. The second approach is to adapt the laser over doping (LOD) process of the phosphor silicate glass (PSG) to create the selective emitter to the properties of laser patterning and plating. In the third approach, we vary the process step order of front laser patterning and back side aluminum firing. The three approaches show very promising results. Efficiencies higher than 22% and open-circuit voltage V-OC values of close to 680 mV are reached on a cell area of 251,99cm(2). Overall the values excel the reference values obtained with screen printing and firing of Ag-paste. For future developments, V-OC values between 685 mV and 690 mV and efficiencies around 22.5% seem very likely.

In this work the first All Copper NICE (New Industrial Solar Cell Encapsulation) modules with solder-free ribbon to finger interconnections are presented. Experiments were conducted to investigate if silver can be fully omitted from solar cells with copper plated fingers in combination with the NICE module technology. We could show that silver flash plating, front and rear silver busbars or pads can be omitted without compromising series resistance or module performance. All Copper NICE modules were manufactured with fillfactors up to 76.8 %.

This paper presents first results of combining two promising future technologies: i) metal catalyzed textured diamond-wire sawn (DWS) mc-Si wafers and ii) nickel-copper-silver (Ni/CuAg) plated front contact processing. Results of first optimizations of laser patterning, annealing and module string soldering are presented. A 60-cell module with a power output of 266 W was successfully manufactured. The pseudo fill-factor (pFF) has been identified as the parameter with the highest potential for further improvements. A very promising approach is moving from an emitter profile that is mainly adapted to silver paste properties to an optimized emitter profile for Ni/Cu/Ag-plated contacts. The idea is to reduce the surface doping concentration (reduces Auger recombination) and increase the junction depth (increased pFF and FF).

In this work, we highlight the benefits of alternative plating routes compared to the standard plating route primarily discussed in literature and currently introduced in pilot production [1, 2]. The common plating route starts with the laser ablation of the front side grid after rear side Al-printing and firing. Then, an HF dip removes the native oxide for the subsequent light induced nickel-, copper plating (LIP) with a silver capping as a finishing. Afterwards, an annealing step improves the adhesion of the plated grid and its contact resistance. Here, we want to show the advantage of three alternative process routes. In the first alternative route, the laser opening of the front side grid is performed before the firing step. During firing, the laser damage is partly cured and can lead to an increase in open circuit voltage (Voc) of 7 mV on state of the art industrial PERC solar cells. For the second process route, the removal of the native oxide is eliminated. To achieve this, special laser and plating conditions are needed. Finally, for the third alternative process route, the annealing of the plated stack can be combined with a stabilization process suppressing the light induced degradation (LID). The presented alternative routes give new degrees of freedom for process optimizations regarding precursor-induced features such as high laser damage on shallow emitters, parasitic plating (PP) for passivation layers with high pinhole density or LID.

The aim of this work was to demonstrate the advantages of the Ni/Cu/Ag plating process when the number of busbars on the solar cell is increased. Cells with four and five busbars were processed and compared to those with three in respect of efficiency, finger and solder adhesion. It is shown that the efficiency can be increased by 0.15%, while the finger adhesion remains the same or improves and the solder adhesion remains mostly greater than 1 N/mm2, if the number of busbars is increased from 3 to 4 or 5. The mass of metal deposited can be reduced by up to 30% for 5 busbars compared to that required for 3 busbars. Furthermore, it is estimated that the cost of metallisation can be reduced from 9 €ct/wafer for three busbars to 8.6 €ct/wafer for five busbars.

Until today, most industrial c-Si solar cells have been limited by front emitter and front metal contact properties. This study demonstrates that laser ablation and inline plating of nickel and copper followed by inline thermal annealing results in improved performance and reduced cost. Stable efficiencies exceeding 20.8% on p-type PERC CZ-Si solar cells have been independently confirmed by FhG-ISE CalLab. Average fill factors up to 80.8% have been demonstrated on large-area solar cells with a homogeneous emitter P surface concentration below 4 × 10 19 P/cm 3 . Reliable module performance according to the IEC61215 standard is reported.

Silicon solar cells are the dominating technology in photovoltaics (PV) industry and have a market share of more than 85% of the modules produced for roof top installations.

In this paper, we investigate different industrial applicable cleaning sequences on test wafers and PERC solar cells in comparison to a laboratory type RCA clean. The cleaning sequences pSC1, HF/HCl, HF/O3 and HF/O3 show lifetimes between 1ms and 2ms which is comparable to a laboratory type RCA clean corresponding to a surface recombination velocity Spass below 15cm/s. The pSC1, HF/HCl clean achieves lifetimes around 1ms, whereas the PSG-etch shows poor cleaning quality with lifetimes around 500μs. Reference PERC cells using a rear protection layer before texturing and diffusion demonstrate efficiencies up to 20.4% for the cleaning sequence pSC1, HF/HCl prior to passivation which is comparable to the RCA clean. The HF/O3 cleans result in lower PERC efficiencies up to 20.0% mainly due to a lower Fill Factor which is likely caused by etching of the emitter and hence increased contact resistance. Investigations of polished test wafers show that the cleaning sequences pSC1, HF/HCl, HF-Dip and pSC1, HF/HCl, HF/O3 are able to sufficiently remove porous silicon from the front side and simultaneously allowing excellent rear surface passivation. A first batch of PERC solar cell results with polished rear surface post texturing and POCl3 diffusion achieves efficiencies of up to 20.7% when applying an RCA clean. However, the pSC1, HF/HCl and pSC1 HF/O3 still exhibit significantly lower efficiencies since in this batch the porous silicon of the emitter was not yet sufficiently removed, which is subject to further optimization.

Simple two-step wet-chemical cleans composed of an oxidizing step with in water dissolved ozone followed by an etching step have been studied for high-efficient hetero-junction silicon solar cell applications. For this purpose flat Si (111) samples passivated with amorphous silicon have been investigated. The effect of nanoroughness of the crystalline silicon surface on the minority carrier lifetime is shown. An influence of the storage time between cleaning and a-Si:H deposition was found and can partly be attributed to changes in surface roughness and native oxide growth.

The influence of temperature on the open-circuit voltage (VOC) of crystalline silicon solar cells is analysed using different semiconductor temperature models with different levels of accuracy. The strongest influence besides the direct dependence of the intrinsic carrier concentration on temperature results from the temperature dependence of the band gap and the effective density of states, while the incomplete ionization plays a minor role for the implied voltage. However incomplete ionization can play an important role for the external voltage at temperatures below 50K due to imperfect selectivity of the emitter and back surface field. The observed saturation of VOC towards low temperatures is caused by the effective density of states. The temperature dependence from 80K to 300K and the intensity dependence as a function of temperature and illumination density were measured on a silicon wafer solar cell resulting in a maximum voltage of 1012mV at T=85.8K. The measured values could be well described by theory.

Comparison of the open-circuit voltage (external voltage V(oc,ext)) determined by Suns-V(oc) measurements with the implied voltage V(oc, impl) determined by transient photoconductance decay lifetime measurements can yield a quick and easy analysis of silicon heterojunction (SHJ) solar cells, especially in regard to finding the optimum doping concentration of the emitter layer [or back surface field (BSF)]. A sufficiently high doping concentration of the emitter and BSF is mandatory to extract the internal Fermi-level splitting and thus the internal voltage, at the solar cell contacts. However increasing the concentration of doping gases during the deposition of doped amorphous silicon layers results in a reduction of the interface passivation quality and Voc, impl. The best trade off is realized when the ratio of V(oc,ext) to V(oc,impl) (external/internal V(oc)-ratio zeta) reaches a saturation value near 1 upon increasing the doping concentration. AFORS-HET (Automat FOR Simulation of HETerostructures) simulations resulted in the conclusion that the characteristics of the external/internal Voc-ratio are mainly determined by the active doping concentration (doping minus defect concentration). (C) 2011 American Institute of Physics. [doi:10.1063/1.3650255]